Mixed-Signal VLSI Design Course Code: EE719 Department: Electrical - - PowerPoint PPT Presentation

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Mixed-Signal VLSI Design Course Code: EE719 Department: Electrical Engineering Lecture 10: February 03, 2020

Instructor Name: M. Shojaei Baghini E-Mail ID: mshojaei@ee.iitb.ac.in

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IIT-Bombay Lecture 10 M. Shojaei Baghini

Module 10 Precision and Speed Considerations Unity Gain Flip Around T&H

References

• Chapter: Introduction to Switched capacitor Circuits

Design of Analog CMOS Integrated Circuits, by Behzad Razavi Second edition, 2017

• Chapter: Switched Capacitor Circuits

Analog integrated circuit design by T. Chan Carusone David A. Johns and Ken Martin, John Wiley & Sons, 2012.

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IIT-Bombay Lecture 10 M. Shojaei Baghini

Sample Hold Unity Gain T&H Circuit with Buffer

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IIT-Bombay Lecture 10 M. Shojaei Baghini

Unity Gain T&H Circuit with Buffer – Hold Mode Accuracy

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IIT-Bombay Lecture 10 M. Shojaei Baghini

Unity Gain T&H Circuit with Buffer – Transient Behavior at the Beginning of Hold Mode

• CL is included (assumption: Cin << CH and CL), otherwise?
• V0 is the sampled value on CH.

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IIT-Bombay Lecture 10 M. Shojaei Baghini

Transient Behavior at the Beginning of Hold Mode Assumption 1: OTA doesn’t slew.

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IIT-Bombay Lecture 10 M. Shojaei Baghini

Transient Behavior at the Beginning of Hold Mode Assumption 1: OTA doesn’t slew. Assumption: Gm Ro >> 1

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IIT-Bombay Lecture 10 M. Shojaei Baghini

Transient Behavior at the Beginning of Hold Mode Assumption 2: OTA slew.

• OTA slew rate

determines the main delay if slew rate is not high enough.

• Cin << CL è S.R. ≈ ISS/CL

Example schematic

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IIT-Bombay Lecture 10 M. Shojaei Baghini

End of Lecture 10