Mixed-Signal VLSI Design Course Code: EE719 Department: Electrical - PowerPoint PPT Presentation

Mixed-Signal VLSI Design Course Code: EE719 Department: Electrical Engineering Lecture 10: February 03, 2020 Instructor Name: M. Shojaei Baghini E-Mail ID: mshojaei@ee.iitb.ac.in 1

2 2 Module 10 Precision and Speed Considerations Unity Gain Flip Around T&H References - Chapter: Introduction to Switched capacitor Circuits Design of Analog CMOS Integrated Circuits, by Behzad Razavi Second edition, 2017 - Chapter: Switched Capacitor Circuits Analog integrated circuit design by T. Chan Carusone David A. Johns and Ken Martin, John Wiley & Sons, 2012. IIT-Bombay Lecture 10 M. Shojaei Baghini

3 3 Unity Gain T&H Circuit with Buffer Sample Hold IIT-Bombay Lecture 10 M. Shojaei Baghini

4 4 Unity Gain T&H Circuit with Buffer – Hold Mode Accuracy IIT-Bombay Lecture 10 M. Shojaei Baghini

5 5 Unity Gain T&H Circuit with Buffer – Transient Behavior at the Beginning of Hold Mode • C L is included (assumption: C in << C H and C L ), otherwise? • V 0 is the sampled value on C H . IIT-Bombay Lecture 10 M. Shojaei Baghini

6 6 Transient Behavior at the Beginning of Hold Mode Assumption 1: OTA doesn’t slew. IIT-Bombay Lecture 10 M. Shojaei Baghini

7 7 Transient Behavior at the Beginning of Hold Mode Assumption 1: OTA doesn’t slew. Assumption: G m R o >> 1 IIT-Bombay Lecture 10 M. Shojaei Baghini

8 8 Transient Behavior at the Beginning of Hold Mode Assumption 2: OTA slew. Example schematic OTA slew rate • determines the main delay if slew rate is not high enough. Cin << CL è S.R. ≈ I SS /C L • IIT-Bombay Lecture 10 M. Shojaei Baghini

9 9 End of Lecture 10 IIT-Bombay Lecture 10 M. Shojaei Baghini