Mixed-Signal VLSI Design Course Code: EE719 Department: Electrical - - PowerPoint PPT Presentation

▶
mixed signal vlsi design course code ee719 department
SMART_READER_LITE
LIVE PREVIEW

Mixed-Signal VLSI Design Course Code: EE719 Department: Electrical - - PowerPoint PPT Presentation

Aug 14, 2022 549 likes •698 views

Mixed-Signal VLSI Design Course Code: EE719 Department: Electrical Engineering Lecture 41: April 17, 2018 Instructor Name: M. Shojaei Baghini E-Mail ID: mshojaei@ee.iitb.ac.in 1 2 2 Module 52 Importance of DAC in using " Modulator

slide-1
SLIDE 1

1

Mixed-Signal VLSI Design Course Code: EE719 Department: Electrical Engineering Lecture 41: April 17, 2018

Instructor Name: M. Shojaei Baghini E-Mail ID: mshojaei@ee.iitb.ac.in

slide-2
SLIDE 2

2 2

IIT-Bombay Lecture 41 M. Shojaei Baghini

Module 52 Importance of DAC in using ∆" Modulator as ADC and Time-Domain Example

References:

  • Section 18.2, Analog Integrated Circuit Design
  • T. C. Caruson, D. A. Johns and K. W. Martin, 2012
  • Prof. Boris Murmann’s Slides
slide-3
SLIDE 3

3 3

IIT-Bombay Lecture 41 M. Shojaei Baghini

1st Order ∆" Modulator

Figure: Boris Murmann

slide-4
SLIDE 4

4 4

IIT-Bombay Lecture 41 M. Shojaei Baghini

DAC Accuracy

  • LPF A(z) cannot distinguish between X(z) and !DAC(z).
  • DAC must be as accurate as the target ADC.

Figure: Boris Murmann

slide-5
SLIDE 5

5 5

IIT-Bombay Lecture 41 M. Shojaei Baghini

Quantizer Output in Single-Bit ∆" Modulator

  • Pulse density and width depend on the signal

level (modulation)

  • Numerical example in the class
slide-6
SLIDE 6

6 6

IIT-Bombay Lecture 41 M. Shojaei Baghini

Quantization Error in Single-Bit ∆" Modulator with Ideal DAC

  • Quantization noise is not a perfect random noise and depends on

the input.

  • shaped quantization noise contains spurious tones (some of them

will be in the signal band)

  • Impact: practical SQNR < ideal SQNR

Figure: Boris Murmann

slide-7
SLIDE 7

7 7

IIT-Bombay Lecture 41 M. Shojaei Baghini

What About Single-bit DAC with a Single-bit Quantizer (Using a Comparator)?

Figures: Boris Murmann

How much will be the SQNR?

slide-8
SLIDE 8

8 8

IIT-Bombay Lecture 41 M. Shojaei Baghini

DAC Trimming

DAC Calibration Example: Trimming or calibration by applying correction values to each level using auxiliary DAC

slide-9
SLIDE 9

9 9

IIT-Bombay Lecture 41 M. Shojaei Baghini

Module 53 Introduction to Circuit Level Implementation of ∆" Modulator

References:

  • Section 18.2, Analog Integrated Circuit Design
  • T. C. Caruson, D. A. Johns and K. W. Martin, 2012
  • Prof. Boris Murmann’s Slides
slide-10
SLIDE 10

10 10

IIT-Bombay Lecture 41 M. Shojaei Baghini

1st Order ∆" Modulator

Figure: Boris Murmann

slide-11
SLIDE 11

11 11

IIT-Bombay Lecture 41 M. Shojaei Baghini

Small Signal Bock Diagram of 1st Order Modulator with Generic Levels for the DAC Outputs

Figure: K. Martin’s book

  • Vref/2 and –Vref/2 will be in general VQL and VQH.
slide-12
SLIDE 12

12 12

IIT-Bombay Lecture 41 M. Shojaei Baghini

Fully Differential Configuration

Figure: Boris Murmann

Vin

+

Vin

  • Vref

+

Vref

  • Vout

Vout Vout

V"#$

slide-13
SLIDE 13

13 13

IIT-Bombay Lecture 41 M. Shojaei Baghini

End of Lecture 41