Mixed-Signal VLSI Design Course Code: EE719 Department: Electrical - PowerPoint PPT Presentation

Mixed-Signal VLSI Design Course Code: EE719 Department: Electrical Engineering Lecture 41: April 17, 2018 Instructor Name: M. Shojaei Baghini E-Mail ID: mshojaei@ee.iitb.ac.in 1

2 2 Module 52 Importance of DAC in using ∆" Modulator as ADC and Time-Domain Example References: - Section 18.2, Analog Integrated Circuit Design T. C. Caruson, D. A. Johns and K. W. Martin, 2012 - Prof. Boris Murmann’s Slides IIT-Bombay Lecture 41 M. Shojaei Baghini

3 3 1st Order ∆" Modulator Figure: Boris Murmann IIT-Bombay Lecture 41 M. Shojaei Baghini

4 4 DAC Accuracy Figure: Boris Murmann LPF A(z) cannot distinguish between X(z) and ! DAC (z). • DAC must be as accurate as the target ADC. • IIT-Bombay Lecture 41 M. Shojaei Baghini

5 5 Quantizer Output in Single-Bit ∆" Modulator Pulse density and width depend on the signal • level (modulation) Numerical example in the class • IIT-Bombay Lecture 41 M. Shojaei Baghini

6 6 Quantization Error in Single-Bit ∆" Modulator with Ideal DAC Figure: Boris Murmann Quantization noise is not a perfect random noise and depends on • the input. shaped quantization noise contains spurious tones (some of them • will be in the signal band) Impact: practical SQNR < ideal SQNR • IIT-Bombay Lecture 41 M. Shojaei Baghini

7 7 What About Single-bit DAC with a Single-bit Quantizer (Using a Comparator)? How much will be the SQNR? Figures: Boris Murmann IIT-Bombay Lecture 41 M. Shojaei Baghini

8 8 DAC Trimming DAC Calibration Example: Trimming or calibration by applying correction values to each level using auxiliary DAC IIT-Bombay Lecture 41 M. Shojaei Baghini

9 9 Module 53 Introduction to Circuit Level Implementation of ∆" Modulator References: - Section 18.2, Analog Integrated Circuit Design T. C. Caruson, D. A. Johns and K. W. Martin, 2012 - Prof. Boris Murmann’s Slides IIT-Bombay Lecture 41 M. Shojaei Baghini

10 10 1st Order ∆" Modulator Figure: Boris Murmann IIT-Bombay Lecture 41 M. Shojaei Baghini

11 11 Small Signal Bock Diagram of 1 st Order Modulator with Generic Levels for the DAC Outputs Figure: K. Martin’s book • V ref /2 and –V ref /2 will be in general V QL and V QH . IIT-Bombay Lecture 41 M. Shojaei Baghini

12 12 Fully Differential Configuration V in + V out V ref + V "#$ V out V ref - V out V in - Figure: Boris Murmann IIT-Bombay Lecture 41 M. Shojaei Baghini

13 13 End of Lecture 41 IIT-Bombay Lecture 41 M. Shojaei Baghini