Mixed-Signal VLSI Design Course Code: EE719 Department: Electrical Engineering Lecture 9: January 30, 2020 Instructor Name: M. Shojaei Baghini E-Mail ID: mshojaei@ee.iitb.ac.in 1
2 2 Module 9 SC Circuits and Correspondence Between CT and DT Circuits References - Chapter: Switched Capacitor Circuits Analog integrated circuit design by T. Chan Carusone David A. Johns and Ken Martin, John Wiley & Sons, 2012. - Chapter: Introduction to Switched capacitor Circuits Design of Analog CMOS Integrated Circuits, by Behzad Razavi, Second edition, 2017 IIT-Bombay Lecture 9 M. Shojaei Baghini
3 3 Correspondence between Continuous-Time Filters and Switched-Capacitor Filters • Example: FE Approximation Sampling Vout at f 1 • Consecutive f 1 and f 2 as • one time stamp - 1 C 1 Z = - ´ H ( Z ) - - 1 C 2 1 Z IIT-Bombay Lecture 09 M. Shojaei Baghini
4 4 Forward Euler Approximation Switched Capacitor Integrator – Generic Expression w C C - j - - 1 T 1 e 2 ( ) C C W - W = ´ = = j T j T H e e 2 2 - W w - j T æ ö 1 e ´ ç ÷ j 2 f sin s è 2 ø w w C 1 - j 2 - ´ ´ 1 e 2 w w æ ö C j ç ÷ sin 2 è 2 ø Question: How do magnitude and phase plots look like in w domain as compared to W domain (continuous-time Fourier frequency)? IIT-Bombay Lecture 09 M. Shojaei Baghini
5 5 Correspondence between Continuous-Time Filters and Switched-Capacitor Filters • Example: BE Approximation Sampling Vout at f 2 • Consecutive f 1 and f 2 as • one time stamp Bottom plate switching IIT-Bombay Lecture 09 M. Shojaei Baghini
6 6 Correspondence Between Continuous-Time and Switched-Capacitor Filters – Example with Finite Zero of the TF IIT-Bombay Lecture 09 M. Shojaei Baghini
7 7 Continuation of the Example CT to DT conversion BE Approximation ( ) + - C Z C 1 Z 1 = - H ( Z ) A ( ) + - C Z C 2 Z 1 B IIT-Bombay Lecture 09 M. Shojaei Baghini
8 8 Continuation of the Example IIT-Bombay Lecture 09 M. Shojaei Baghini
9 9 Continuation of the Example – Replacing Resistors with Switches IIT-Bombay Lecture 09 M. Shojaei Baghini
10 10 Calculating Capacitor Ratios Case I: |pole| ´ T and |zero| ´ T ≪ 1 for all poles and zeros , i.e. w T ≪ 1 (T=1/fs ) IIT-Bombay Lecture 09 M. Shojaei Baghini
11 11 Calculating Capacitor Ratios If |pole| ´ T and |zero| ´ T ≪ 1 for all poles and zeros , i.e. w T ≪ 1 (T=1/f s ) IIT-Bombay Lecture 09 M. Shojaei Baghini
12 12 Numerical Example First order SC low-pass filter with sampling frequency fs • = 1MS/s -3dB cut off frequency fc = 20kHz • Zero gain at z = 0 (i.e. zero at very high continuous-time • frequency, which means only a single pole and no finite • zero in discrete-time frequency domain. DC gain = 10 • Zero gain at s = - ¥ Þ Zero at Z=0 Þ C1=0 IIT-Bombay Lecture 09 M. Shojaei Baghini
13 13 Calculating Capacitor Ratios (continued) Zero gain at s = - ¥ Þ Zero at Z=0 Þ C1=0 ( ) + - C Z C 1 Z 1 = - ) Þ H ( Z ) A ( + - C Z C 2 Z 1 B w ( ) j / 2 C Z C e d w = - Þ j » - H ( Z ) A H e A d ( ) + - æ ö C Z C 2 Z 1 C 1 C ç ÷ + + w B B 1 j 2 ç ÷ d 2 C è ø B IIT-Bombay Lecture 09 M. Shojaei Baghini
14 14 Calculating Capacitor Ratios (continued) ( ) ( ) w + - j / 2 C Z C 1 Z 1 C e d w = - Þ j » - H ( Z ) A H e A d ( ) + - æ ö C Z C 2 Z 1 C 1 C ç ÷ + + w B B 1 j 2 ç ÷ d 2 C è ø B ------------------------------------------------------------------------- -3dB cut off frequency fc = 20kHz = fs/50 ------------------------------------------------------------------------- DC gain =10 Þ C A /C B = 10 IIT-Bombay Lecture 09 M. Shojaei Baghini
15 15 End of Lecture 9 IIT-Bombay Lecture 09 M. Shojaei Baghini
Mixed-Signal VLSI Design Course Code: EE719 Department: Electrical Engineering Lecture 10: February 03, 2020 Instructor Name: M. Shojaei Baghini E-Mail ID: mshojaei@ee.iitb.ac.in 1
2 2 Module 10 Precision and Speed Considerations Unity Gain Flip Around T&H References - Chapter: Introduction to Switched capacitor Circuits Design of Analog CMOS Integrated Circuits, by Behzad Razavi Second edition, 2017 - Chapter: Switched Capacitor Circuits Analog integrated circuit design by T. Chan Carusone David A. Johns and Ken Martin, John Wiley & Sons, 2012. IIT-Bombay Lecture 10 M. Shojaei Baghini
3 3 Unity Gain T&H Circuit with Buffer Sample Hold IIT-Bombay Lecture 10 M. Shojaei Baghini
4 4 Unity Gain T&H Circuit with Buffer – Hold Mode Accuracy IIT-Bombay Lecture 10 M. Shojaei Baghini
5 5 Unity Gain T&H Circuit with Buffer – Transient Behavior at the Beginning of Hold Mode • C L is included (assumption: C in << C H and C L ), otherwise? • V 0 is the sampled value on C H . IIT-Bombay Lecture 10 M. Shojaei Baghini
6 6 Transient Behavior at the Beginning of Hold Mode Assumption 1: OTA doesn’t slew. IIT-Bombay Lecture 10 M. Shojaei Baghini
7 7 Transient Behavior at the Beginning of Hold Mode Assumption 1: OTA doesn’t slew. Assumption: G m R o >> 1 IIT-Bombay Lecture 10 M. Shojaei Baghini
8 8 Transient Behavior at the Beginning of Hold Mode Assumption 2: OTA slew. Example schematic OTA slew rate • determines the main delay if slew rate is not high enough. Cin << CL è S.R. ≈ I SS /C L • IIT-Bombay Lecture 10 M. Shojaei Baghini
9 9 End of Lecture 10 IIT-Bombay Lecture 10 M. Shojaei Baghini
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