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Mixed-Signal VLSI Design Course Code: EE719 Department: Electrical Engineering Lecture 9: January 30, 2020 Instructor Name: M. Shojaei Baghini E-Mail ID: mshojaei@ee.iitb.ac.in 1 2 2 Module 9 SC Circuits and Correspondence Between CT and

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Mixed-Signal VLSI Design Course Code: EE719 Department: Electrical Engineering Lecture 9: January 30, 2020

Instructor Name: M. Shojaei Baghini E-Mail ID: mshojaei@ee.iitb.ac.in

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IIT-Bombay Lecture 9 M. Shojaei Baghini

Module 9 SC Circuits and Correspondence Between CT and DT Circuits

References

Chapter: Switched Capacitor Circuits

Analog integrated circuit design by T. Chan Carusone David A. Johns and Ken Martin, John Wiley & Sons, 2012.

Chapter: Introduction to Switched capacitor Circuits

Design of Analog CMOS Integrated Circuits, by Behzad Razavi, Second edition, 2017

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IIT-Bombay Lecture 09 M. Shojaei Baghini

Correspondence between Continuous-Time Filters and Switched-Capacitor Filters

Example: FE Approximation
Sampling Vout at f1
Consecutive f1 and f2 as
ne time stamp

1 1

1 2 1 ) (

Z Z C C Z H

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IIT-Bombay Lecture 09 M. Shojaei Baghini

Forward Euler Approximation

Switched Capacitor Integrator – Generic Expression

( )

÷ ø ö ç è æ ´ ´

÷ ø ö ç è æ ´

=

2 sin 2 1 2 sin 2 1

2 2 1 2 2 1 2 1

w w w w

w w

j e C C f j e C C e T C C e e H

j s j T j T j T j

Question: How do magnitude and phase plots look like in w domain as compared to W domain (continuous-time Fourier frequency)?

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IIT-Bombay Lecture 09 M. Shojaei Baghini

Correspondence between Continuous-Time Filters and Switched-Capacitor Filters

Example: BE Approximation
Sampling Vout at f2
Consecutive f1 and f2 as
ne time stamp

Bottom plate switching

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IIT-Bombay Lecture 09 M. Shojaei Baghini

Correspondence Between Continuous-Time and Switched-Capacitor Filters – Example with Finite Zero of the TF

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IIT-Bombay Lecture 09 M. Shojaei Baghini

Continuation of the Example CT to DT conversion BE Approximation ( ) ( )

1 2 1 1 ) (

Z C Z C Z C Z C Z H

B A

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IIT-Bombay Lecture 09 M. Shojaei Baghini

Continuation of the Example

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IIT-Bombay Lecture 09 M. Shojaei Baghini

Continuation of the Example – Replacing Resistors with Switches

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IIT-Bombay Lecture 09 M. Shojaei Baghini

Calculating Capacitor Ratios

Case I: |pole|´T and |zero| ´ T ≪ 1 for all poles and zeros , i.e. wT ≪ 1 (T=1/fs )

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IIT-Bombay Lecture 09 M. Shojaei Baghini

Calculating Capacitor Ratios

If |pole|´T and |zero|´T ≪ 1 for all poles and zeros , i.e. wT ≪ 1 (T=1/fs )

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IIT-Bombay Lecture 09 M. Shojaei Baghini

Numerical Example

First order SC low-pass filter with sampling frequency fs

= 1MS/s

3dB cut off frequency fc = 20kHz
Zero gain at z = 0 (i.e. zero at very high continuous-time
frequency, which means only a single pole and no finite

zero in discrete-time frequency domain.

DC gain = 10

Zero gain at s = -¥ Þ Zero at Z=0 Þ C1=0

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IIT-Bombay Lecture 09 M. Shojaei Baghini

Calculating Capacitor Ratios (continued)

Zero gain at s = -¥ Þ Zero at Z=0 Þ C1=0

( )

d B j B A j B A

C C j e C C e H Z C Z C Z C Z H

d d

w

w w

÷ ÷ ø ö ç ç è æ + +

Þ

2 2 /

2 1 1 1 2 ) (

( ) ( ) Þ

1 2 1 1 ) ( Z C Z C Z C Z C Z H

B A

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IIT-Bombay Lecture 09 M. Shojaei Baghini

Calculating Capacitor Ratios (continued)

3dB cut off frequency fc = 20kHz = fs/50
DC gain =10 Þ CA/CB = 10

( ) ( )

( )

d B j B A j B A

C C j e C C e H Z C Z C Z C Z C Z H

d d

w

w w

÷ ÷ ø ö ç ç è æ + +

Þ

2 2 /

2 1 1 1 2 1 1 ) (

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IIT-Bombay Lecture 09 M. Shojaei Baghini

End of Lecture 9

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Mixed-Signal VLSI Design Course Code: EE719 Department: Electrical Engineering Lecture 10: February 03, 2020

Instructor Name: M. Shojaei Baghini E-Mail ID: mshojaei@ee.iitb.ac.in

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IIT-Bombay Lecture 10 M. Shojaei Baghini

Module 10 Precision and Speed Considerations Unity Gain Flip Around T&H

References

Chapter: Introduction to Switched capacitor Circuits

Design of Analog CMOS Integrated Circuits, by Behzad Razavi Second edition, 2017

Chapter: Switched Capacitor Circuits

Analog integrated circuit design by T. Chan Carusone David A. Johns and Ken Martin, John Wiley & Sons, 2012.

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IIT-Bombay Lecture 10 M. Shojaei Baghini

Sample Hold Unity Gain T&H Circuit with Buffer

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IIT-Bombay Lecture 10 M. Shojaei Baghini

Unity Gain T&H Circuit with Buffer – Hold Mode Accuracy

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IIT-Bombay Lecture 10 M. Shojaei Baghini

Unity Gain T&H Circuit with Buffer – Transient Behavior at the Beginning of Hold Mode

CL is included (assumption: Cin << CH and CL), otherwise?
V0 is the sampled value on CH.

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IIT-Bombay Lecture 10 M. Shojaei Baghini

Transient Behavior at the Beginning of Hold Mode Assumption 1: OTA doesn’t slew.

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IIT-Bombay Lecture 10 M. Shojaei Baghini

Transient Behavior at the Beginning of Hold Mode Assumption 1: OTA doesn’t slew. Assumption: Gm Ro >> 1

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IIT-Bombay Lecture 10 M. Shojaei Baghini

Transient Behavior at the Beginning of Hold Mode Assumption 2: OTA slew.

OTA slew rate

determines the main delay if slew rate is not high enough.

Cin << CL è S.R. ≈ ISS/CL

Example schematic

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IIT-Bombay Lecture 10 M. Shojaei Baghini

Mixed-Signal VLSI Design Course Code: EE719 Department: Electrical Engineering Lecture 9: January 30, 2020

Instructor Name: M. Shojaei Baghini E-Mail ID: mshojaei@ee.iitb.ac.in

Module 9 SC Circuits and Correspondence Between CT and DT Circuits

References

Analog integrated circuit design by T. Chan Carusone David A. Johns and Ken Martin, John Wiley & Sons, 2012.

Design of Analog CMOS Integrated Circuits, by Behzad Razavi, Second edition, 2017

Correspondence between Continuous-Time Filters and Switched-Capacitor Filters

1 2 1 ) (

Z Z C C Z H

Forward Euler Approximation

Switched Capacitor Integrator – Generic Expression

( )

÷ ø ö ç è æ ´ ´

÷ ø ö ç è æ ´

=

2 sin 2 1 2 sin 2 1

w w w w

j e C C f j e C C e T C C e e H

Question: How do magnitude and phase plots look like in w domain as compared to W domain (continuous-time Fourier frequency)?

Correspondence between Continuous-Time Filters and Switched-Capacitor Filters

Bottom plate switching

Correspondence Between Continuous-Time and Switched-Capacitor Filters – Example with Finite Zero of the TF

Continuation of the Example CT to DT conversion BE Approximation ( ) ( )

1 2 1 1 ) (

Z C Z C Z C Z C Z H

Continuation of the Example

Continuation of the Example – Replacing Resistors with Switches

Calculating Capacitor Ratios

Case I: |pole|´T and |zero| ´ T ≪ 1 for all poles and zeros , i.e. wT ≪ 1 (T=1/fs )

Calculating Capacitor Ratios

If |pole|´T and |zero|´T ≪ 1 for all poles and zeros , i.e. wT ≪ 1 (T=1/fs )

Numerical Example

= 1MS/s

zero in discrete-time frequency domain.

Zero gain at s = -¥ Þ Zero at Z=0 Þ C1=0

Calculating Capacitor Ratios (continued)

Zero gain at s = -¥ Þ Zero at Z=0 Þ C1=0

( )

( )

C C j e C C e H Z C Z C Z C Z H

w

÷ ÷ ø ö ç ç è æ + +

Þ

2 1 1 1 2 ) (

( ) ( ) Þ

1 2 1 1 ) ( Z C Z C Z C Z C Z H

Calculating Capacitor Ratios (continued)

( ) ( )

( )

C C j e C C e H Z C Z C Z C Z C Z H

w

÷ ÷ ø ö ç ç è æ + +

Þ

2 1 1 1 2 1 1 ) (

End of Lecture 9

Mixed-Signal VLSI Design Course Code: EE719 Department: Electrical Engineering Lecture 10: February 03, 2020

Instructor Name: M. Shojaei Baghini E-Mail ID: mshojaei@ee.iitb.ac.in

Module 10 Precision and Speed Considerations Unity Gain Flip Around T&H

References

Design of Analog CMOS Integrated Circuits, by Behzad Razavi Second edition, 2017

Analog integrated circuit design by T. Chan Carusone David A. Johns and Ken Martin, John Wiley & Sons, 2012.

Sample Hold Unity Gain T&H Circuit with Buffer

Unity Gain T&H Circuit with Buffer – Hold Mode Accuracy

Unity Gain T&H Circuit with Buffer – Transient Behavior at the Beginning of Hold Mode

Transient Behavior at the Beginning of Hold Mode Assumption 1: OTA doesn’t slew.

Transient Behavior at the Beginning of Hold Mode Assumption 1: OTA doesn’t slew. Assumption: Gm Ro >> 1

Transient Behavior at the Beginning of Hold Mode Assumption 2: OTA slew.

determines the main delay if slew rate is not high enough.

Example schematic

End of Lecture 10