Mixed-Signal VLSI Design Course Code: EE719/EE410 Department: - - PowerPoint PPT Presentation

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Mixed-Signal VLSI Design Course Code: EE719/EE410 Department: - - PowerPoint PPT Presentation

May 19, 2023 398 likes •551 views

Mixed-Signal VLSI Design Course Code: EE719/EE410 Department: Electrical Engineering Semester: Spring 2011 Instructor Name: M. Shojaei Baghini E-Mail ID: mshojaei@ee.iitb.ac.in 1 2 2 Date: March 02, 2011 Date: March 02, 2011 Data

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Mixed-Signal VLSI Design Course Code: EE719/EE410 Department: Electrical Engineering Semester: Spring 2011 Instructor Name: M. Shojaei Baghini E-Mail ID: mshojaei@ee.iitb.ac.in

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IIT-Bombay Lecture 12 M. Shojaei Baghini

Date: March 02, 2011 Date: March 02, 2011

Data Converters

Data Converters

Contents Contents

 Performance Specifications of Data

Converters

 ADC and DAC Architectures  Flash ADC

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IIT-Bombay Lecture 12 M. Shojaei Baghini

Ideal Characteristic of ADC

1 LSB Center point

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IIT-Bombay Lecture 12 M. Shojaei Baghini

Quantization Error in Ideal ADC

FS/2N

For a sine wave signal x(t) and approximate uniform distribution of qe Example: N = 6 bits ⇒ SNR=37.9dB N = 10 bits ⇒ SNR=62.0dB

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IIT-Bombay Lecture 12 M. Shojaei Baghini

Incorporating Nonlinearities of ADC

  • THD (Total Harmonic Distortion)
  • SINAD (or SNDR) (Signal to Noise and Distortion Ratio)

SINAD: Ratio of rms value of the input signal to the rms sum of all other spectral components.

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IIT-Bombay Lecture 12 M. Shojaei Baghini

Frequency Domain - ADC Nonlinearity

Nicolas Gray, National Semiconductor, 2006

FFT fs=200MS/s f0=45.0195MHz Harmonics?

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IIT-Bombay Lecture 12 M. Shojaei Baghini

In general dynamic range is the ratio of largest absolute value of the signal to the smallest absolute value of the signal. In an ideal ADC, dynamic range = 20.log2N ≈ 6NdB. Some times dynamic range is defined as SNR itself. Spurious-Free Dynamic Range (SFDR): Ratio of the input signal to the peak harmonic (or spurious)component. Dynamic Range

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IIT-Bombay Lecture 12 M. Shojaei Baghini

SFDR - Example

Nicolas Gray, National Semiconductor, 2006 Noise floor

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IIT-Bombay Lecture 12 M. Shojaei Baghini

Static and Time Domain Specifications Offset and Gain Error

1 LSB Center point Slope < 2N/FS

(Gain error in codes/per signal unit)

Offset error Offset error

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IIT-Bombay Lecture 12 M. Shojaei Baghini

Static and Time Domain Specifications – DNL (Differential Nonlinearity) of ADC

Understanding Data Converters, TI, 1995

Sometimes only maximum |DNL| is given in data sheets.

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IIT-Bombay Lecture 12 M. Shojaei Baghini

Static and Time Domain Specifications – DNL (Differential Nonlinearity) of DAC

Understanding Data Converters, TI, 1995

Sometimes only maximum |DNL| is given in data sheets.

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IIT-Bombay Lecture 12 M. Shojaei Baghini

Static and Time Domain Specifications – INL (Integrated Nonlinearity)

Understanding Data Converters, TI, 1995

INL is measured after the offset is corrected to zero.

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IIT-Bombay Lecture 12 M. Shojaei Baghini

Main Time Domain Specifications

  • Conversion Time
  • Sampling Rate
  • Sampling-Time Uncertainty
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IIT-Bombay Lecture 12 M. Shojaei Baghini

Flash ADC Architecture and an example considering variations in the resistive network and comparator offset voltages is explained in the lecture.

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IIT-Bombay Lecture 12 M. Shojaei Baghini

End of lecture 12