Electronic System Level Design Modules & Hierarchy in SystemC Maziar Goudarzi
Today Program Modules in SystemC Hierarchical Design in SystemC 2009 ESL Design 2
Why Modules? Advantages Building Block in Design Hierarchy Team Work Design Encapsulation Design Re-use 2009 ESL Design 3
Parts of a Module Ingredients Module Ports Module Signals Internal Data Storage Processes Module Constructors 2009 ESL Design 4
General Syntax for Module Definition Port mode SC_MODULE( module_name ) { sc_in< bool > in ; sc_out< int > out ; sc_inout< float > inout ; Port type sc_signal< char > aSignal ; long l ; // internal data storage void process() { ... } // processes SC_CTOR( module_name ) { ... } }; 2009 ESL Design 5
What is SC_MODULE? Defined in <SystemC>\include\kernel\sc_module.h #define SC_MODULE(user_module_name) \ struct user_module_name : sc_module class sc_module: public sc_object{ ... }; 2009 ESL Design 6
Ports Port modes sc_in< > sc_out< > sc_inout< > Specific to clock ports (only for backward compatibility) sc_in_clk sc_out_clk sc_inout_clk Actually: (look at <systemc>/include/communication/sc_clock_ports.h ) typedef sc_in<bool> sc_in_clk; typedef sc_inout<bool> sc_inout_clk; typedef sc_out<bool> sc_out_clk; 2009 ESL Design 7
Signals Signal Used to connect ports of lower-level modules Correspond to wires Unlike ports, no mode (in, out, inout) required Bi-directional transmission possible Actual direction depends on the connecting ports Syntax sc_signal< signal_type > signal_name ; 2009 ESL Design 8
Connecting Ports & Signals Note: when connecting ports using signals Type of signals and ports must match sc_in< int > intInput; sc_signal< int > intSignal; Port mapping Positional port mapping Named port mapping 2009 ESL Design 9
Positional Port Mapping // filter.h #include "systemc.h" #include "mult.h" #include "coeff.h" #include "sample.h" SC_MODULE(filter) { sample *s1; coeff *c1; mult *m1; sc_signal< int > q, s, c; Module instantiation SC_CTOR(filter) { s1 = new sample ("s1"); // sample.h (*s1)(q,s); SC_MODULE(sample) { Port c1 = new coeff ("c1"); sc_in<int> din; mapping (*c1)(c); sc_out<int> dout; ... m1 = new mult ("m1"); (*m1)(s,c,q); }; } 2009 ESL Design 10 };
Positional Port Mapping (cont’d) Positional port mapping Ports are connected in the same order as in the module definition Orders and number of ports MUST match in the definition and in the instantiation One C++ statement to map all ports Advantage Compactness Good when only having a few ports Disadvantage Lower readability Error prone 2009 ESL Design 11
Named Port Mapping #include "sample.h“ SC_MODULE(filter) { sample *s1; coeff *c1; mult *m1; sc_signal< int > q, s, c; SC_CTOR(filter) { s1 = new sample ("s1"); s1->dout(s); s1->din(q); // sample.h c1 = new coeff ("c1"); SC_MODULE(sample) { c1->out(c); sc_in<int> din; m1 = new mult ("m1"); sc_out<int> dout; m1->a(s); ... m1->b(c); m1->q(q); }; } 2009 ESL Design 12 };
Named Port Mapping (cont’d) Named port mapping Ports can be connected in any order One C++ statement to map each port Advantage Higher readability Lower probability of errors Disadvantage More verbose 2009 ESL Design 13
Port Mapping: Another Positional Mapping Style // filter.h // filter.h #include "systemc.h" #include "systemc.h" #include "mult.h" #include "mult.h" #include "coeff.h" #include "coeff.h" #include "sample.h" #include "sample.h" SC_MODULE(filter) { SC_MODULE(filter) { sample *s1; sample *s1; coeff *c1; coeff *c1; mult *m1; mult *m1; sc_signal< int > q, s, c; sc_signal< int > q, s, c; SC_CTOR(filter) { SC_CTOR(filter) { s1 = new sample ("s1"); s1 = new sample ("s1"); (*s1)(q,s); (*s1) << q <<s; c1 = new coeff ("c1"); c1 = new coeff ("c1"); (*c1)(c); (*c1) << c; m1 = new mult ("m1"); m1 = new mult ("m1"); (*m1)(s,c,q); (*m1) << s << c << q; } } 2009 ESL Design 14 } }
Hierarchical Design Key to implementing complex designs Divide and conquer Two approaches Bottom-up design Top-down design 2009 ESL Design 15
Hierarchical Design (cont’d) Two basic styles for connecting modules One module connected to the other one In the same level of hierarchy Example • The filter example: sample, coeff, and mult modules One module inside the other one Hierarchical design Example: A register consisting of several DFFs 2009 ESL Design 16
Hierarchical Modules Example Register Module Register q d DFF DFF DFF DFF clk 2009 ESL Design 17
Hierarchical Modules Example (cont’d) # include "dff.h“ Register q d DFF #define REG_WIDTH 10 DFF SC_MODULE(reg) { DFF sc_in<bool> d[REG_WIDTH]; DFF sc_in<bool> clk; clk sc_out<bool> q[REG_WIDTH]; DFF *ff[REG_WIDTH]; SC_CTOR(reg) { for(int i=0; i<REG_WIDTH; i++) { ff[i] = new DFF( itoa(i,NULL,10) ); ff[i]->d( d[i] ); Direct port-to-port ff[i]->q( q[i] ); connection (no signal) ff[i]->clk( clk ); } } 2009 ESL Design 18 };
Rules for Connecting Ports In hierarchical design Port modes must match sc_in<> to sc_in<> sc_out<> to sc_out<> sc_inout<> to sc_inout<> 2009 ESL Design 19
Parts of a Module (cont’d) Ingredients Module Ports Module Signals Internal Data Storage Processes Module Constructors 2009 ESL Design 20
Internal Data Storage: Counter with Synchronous-Load SC_MODULE(counter) { din dout sc_in<bool> load; Counter w. sc_in<int> din; sync. load sc_in<bool> clock; sc_out<int> dout; load clock int count_val; void counter::count_up() { void count_up(); if (load) count_val = din; SC_CTOR(counter) { else SC_METHOD(count_up); count_val++; sensitive_pos << clock; dout = count_val; } } }; 2009 ESL Design 21
Internal Data Storage (cont’d) Can be any C++ type or user-defined type Visible outside the module Remember: SC_MODULE is a C++ struct NOTE: C++ allows it, but DO NOT change values of internal variables from outside a module 2009 ESL Design 22
Process Implement the real functionality of the module Sensitivity list: List of ports that this process is sensitive to Registered with “SystemC Simulation Kernel” at run -time Name of the process + its sensitivity list Place & time: at module instantiation time (when the constructor is called) Called by “SystemC Simulation Kernel” whenever one of the ports in the “sensitivity list” changes value Executes sequentially until return() or wait() 2009 ESL Design 23
Process (cont’d) // dff.h #include "systemc.h" SC_MODULE(dff) { sc_in<bool> din; sc_in<bool> clock; sc_out<bool> dout; void doit() { dout = din; } SC_CTOR(dff) { SC_METHOD(doit); sensitive_pos << clock; } }; 2009 ESL Design 24
Module Constructor Register module Processes, and their sensitivity list with “SystemC Kernel” Create and initialize “Internal Data Structures” of the module Initialize Internal Data Storage An “instance name” is passed to the constructor at instantiation time Each instantiated module (even from the same SC_MODULE type) can have its own name Helps in reporting debug, error, and information messages from the module 2009 ESL Design 25
Module Constructor (cont’d) // ram.h #include "systemc.h" SC_MODULE(ram) { sc_in<int> addr; sc_in<int> datain; sc_in<bool> rwb; sc_out<int> dout; int memdata[64]; // local memory storage int i; void ramread(); void ramwrite(); SC_CTOR(ram){ Process declaration SC_METHOD(ramread); sensitive << addr << rwb; SC_METHOD(ramwrite) sensitive << addr << datain << rwb; for (i=0; i++; i<64) memdata[i] = 0; } }; 2009 ESL Design 26
What we learned today Module concept in SystemC and its ingredients Hierarchical Design in SystemC Reading material Chapters 1, 2, and 4 of “A SystemC Primer” book Further reading: SystemC ver. 2.0 User’s Guide ( Chapters 1 2 3) 2009 ESL Design 27
Assignment 1 Design a 4-bit adder using only basic gates (i.e., AND, OR, NOT, NAND, NOR gate) and hierarchical design (top-down or bottom-up) Write a complete test bench for your adder and compile and simulate your model. Due date: Sunday, Mehr 26 th Submit one compressed file (zip/rar) 2009 ESL Design 28
Other Notes Course project phases set. 4 phases. 2 Aban: Deadline for phase 0 of course project: 1-page document Your group members for course project The definition of the project Rough schedule 2009 ESL Design 29
Recommend
More recommend
