CENG 342 Digital Systems Generate Statement and Using Components - - PowerPoint PPT Presentation

CENG 342 – Digital Systems

Generate Statement and Using Components Larry Pyeatt

SDSM&T

The generate Statement

Allows the programmer to instantiate an “array” of entities/components. Syntax:

1 label: for parameter in range generate 2

concurrent statements

3 end generate label;

The generate parameter may be used to index array-type signals associated with component ports.

The generate Statement

Suppose you have a one-bit register with the following entity definition:

1 entity reg_1_bit is 2

port( din: in std_logic,

3

clk: in std_logic,

4

reset: in std_logic,

5

dout: out std_logic);

6 end entity reg;

You can now create a generic register that is made up of one-bit registers.

1 entity generic_register is generic(N : natural := 8 ) 2

port(input: in std_logic_vector(N-1 downto 0),

3

clk: in std_logic,

4

reset: in std_logic,

5

• utput: out std_logic_vector(N-1 downto 0));

6 end entity reg; 7 8 architecture gen of generic_register is 9 begin 10

gen_reg: for I in N-1 downto 0 generate

11

regI : entity reg_1_bit port map

12

(din=>input(I), clk=>clk, reset=>reset, dout=>output(I));

13

end generate gen_reg;

14 end architecture gen;

Components

Sometimes it is useful to declare the ports of a device without specifying the entity. The exact entity to be used will be defined later. Think of component as declaring a socket which can accept different entity/architecture pairs (as long as they have the same port mapping). The syntax is the same as the syntax for an entity, but components cannot have architectures.

Component Example – Part 1

1 -- declare a silly little entity and give it an architecture 2 entity exor is 3

port (

4

in1: in bit;

5

in2: in bit;

6

• ut1:
• ut bit

7

);

8 end entity; 9 10 architecture arch of exor is 11 begin 12

• ut1 <= in1 xor in2;

13 end architecture;

Component Example – Part 2

15 -- declare a testbench and give it an architecture 16 entity exor_test is 17 end entity; 18 19 architecture foo of exor_test is 20

component x is

• - define a component that matches exor

21

port (a: in bit;

22

b: in bit;

23

c: out bit);

24

end component;

25

• - signals for the test

26

signal a, b, c: bit;

27 begin 28

• - instantiate component

29

TARG: x port map (a => a,b => b,c => c);

30 31

STIMULUS:

32

process

33

begin

34

wait for 2 ns; a <= ’1’;

35

wait for 2 ns; b <= ’1’;

36

wait for 2 ns; a <= ’0’;

37

wait for 2 ns; b <= ’0’;

38

wait for 2 ns; a <= ’1’;

39

wait for 2 ns;

40

wait;

41

end process;

42 end architecture;

Component Example – Part 3

44 -- create configuration for entity exor_test 45 -- this specifies which entity should be used for component x in 46 -- architecure foo of component exor_test, and of course this 47 -- configuration also has a name: conf 48 configuration conf of exor_test is 49

for foo

50

for TARG: x use entity work.exor(arch)

51

port map (

52

in1 => a,

53

in2 => b,

54

• ut1 => c

55

);

56

end for;

57

end for;

58 end configuration conf;