III-V CMOS: the key to sub-10 nm electronics? J. A. del Alamo - - PowerPoint PPT Presentation

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III-V CMOS:

the key to sub-10 nm electronics?

• J. A. del Alamo

Microsystems Technology Laboratories, MIT

Acknowledgements:

• Sponsors: Intel, FCRP-MSD
• Collaborators: Dae-Hyun Kim, Donghyun Jin, Tae-Woo Kim, Niamh Waldron,

Ling Xia, Dimitri Antoniadis, Robert Chau

• Labs at MIT: MTL, NSL, SEBL

2011 MRS Spring Meeting and Exhibition

Symposium P: Interface Engineering for Post-CMOS Emerging Channel Materials April 25-29, 2011

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Outline

• Why III-Vs for CMOS?
• Lessons from III-V HEMTs
• The challenges for III-V CMOS

– Critical problems

• How will a future 10 nm class III-V FET look like?
• Conclusions

CMOS scaling in the 21st century

• Si CMOS has entered era of “power-constrained scaling”:

– Microprocessor power density saturated at ~100 W/cm2 – Microprocessor clock speed saturated at ~ 4 GHz

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Intel microprocessors

Pop, Nano Res 2010

Transistor scaling requires reduction in supply voltage  Not possible with Si: performance degrades too much

Consequences of Power Constrained Scaling

Power = active power + stand-by power

PA~ f CVDD

2N N ↑  VDD ↓

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#1 goal!

clock frequency transistor capacitance

• perating voltage

transistor count

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How III-Vs allow further VDD reduction?

• Goals of scaling:

– reduce transistor footprint – extract maximum ION for given IOFF

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How III-Vs allow further VDD reduction?

• Goals of scaling:

– reduce transistor footprint – extract maximum ION for given IOFF

• III-Vs:

– higher electron velocity than Si  ION ↑ – tight carrier confinement in quantum well  S ↓  sharp turn on

S D

Etch stopper

Barrier Channel Buffer t ins

Oxide

t ch

Gate

Cap

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InAs High Electron Mobility Transistors

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• QW channel (tch = 10 nm):
• InAs core (tInAs = 5 nm)
• InGaAs cladding
• n,Hall = 13,200 cm2/V-sec
• InAlAs barrier (tins = 4 nm)
• Ti/Pt/Au Schottky gate
• Lg=30 nm

Kim, EDL 2010

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Lg=30 nm InAs HEMT

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• Large current drive: ION>0.5 mA/µm at VDD=0.5 V
• VT = -0.15 V, RS=190 ohm.μm
• High transconductance: gmpk= 1.9 mS/μm at VDD=0.5 V

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Kim, EDL 2010

0.0 0.2 0.4 0.6 0.8 0.0 0.2 0.4 0.6 0.8

0.2 V 0.4 V 0 V

ID [mA/m] VDS [V]

VGS =

• 0.6
• 0.4
• 0.2

0.0 0.2 0.0 0.5 1.0 1.5 2.0

gm [mS/m] VGS [V]

VDS = 0.5 V

10

9

10

10

10

11

10

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10 20 30 40

Frequency [Hz] Gains [dB]

• 1

1 2 3

K

H21 K MSG/MAG Ug

Lg=30 nm InAs HEMT

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• FET with highest fT in any material system
• Only transistor of any kind with both fT and fmax > 640 GHz
• S = 74 mV/dec, DIBL = 80 mV/V, Ion/Ioff ~ 5x103
• All FOMs at VDD=0.5 V

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Kim, EDL 2010

• 1.0
• 0.8
• 0.6
• 0.4
• 0.2

0.0 0.2 0.4 10

• 9

10

• 8

10

• 7

10

• 6

10

• 5

10

• 4

10

• 3

VDS = 0.05 V VDS = 0.5 V

IG ID

VDS = 0.5 V

ID, IG [A/m] VGS [V]

VDS = 0.05 V

fT=644 GHz fmax=681 GHz

VDS=0.5 V, VGS=0.2 V

• FOM that integrates short-channel effects and transport:

ION @ IOFF=100 nA/µm, VDD=0.5 V InAs HEMTs: higher ION for same IOFF than Si

InAs HEMTs: Benchmarking with Si

10 (scaled to VDD=0.5 V) IEDM 2008 Kim EDL 2010

• 1. Very high electron injection velocity at the virtual source

EC vinj

• vinj(InGaAs) increases with InAs fraction in channel
• vinj(InGaAs) > 2vinj(Si) at less than half VDD

Why high ION?

Kim, IEDM 2009 Liu, Springer 2010

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EV

• 2. Sharp subthreshold swing due to quantum-well channel
• Dramatic improvement in short-channel effects in thin

channel devices

Why high ION?

Kim, IPRM 2010

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60 70 80 90 160 40 200 120 80

InAs HEMTs: tch = 5 nm InAs HEMTs: tch = 10 nm In0.7Ga0.3As HEMTs: tch = 13 nm

Subtreshold swing [mV/dec]

Lg [nm]

tins = 4 nm, Lside = 80 nm

state-of-the-art Si

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The Challenges for III-V CMOS: III-V HEMT vs. Si CMOS

• Schottky gate  MOS gate
• Footprint scaling [1000x too big!]

 Need self-aligned design

• p-channel device
• III-V on Si

Intel’s 45 nm CMOS III-V HEMT

Critical issues:

~2 m

• The challenge:

– III-V heterostructures on large-area Si wafers – Thin buffer layer – Low defectivity

• Some notable work:

Aspect Ratio Trapping + Epitaxial Lateral Overgrowth (Amberwave) Fiorenza, ECS 2010

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InAs Nanoribbon MOSFETs on Insulator (UC Berkeley) Ko, Nature 2010

III-V’s on Si

Si SiO2 InAs G S D

XOI InAs MOSFET

Direct III-V MBE on Si (Intel) Hudait, IEDM 2007

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Critical problem: Integration of two different layer structures side-by-side on Si

Key issues:

Fiorenza ECS 2010

• different lattice constants
• planar surface
• compact

The gate stack

• Challenge: metal/high-K oxide gate stack

– Fabricated through ex-situ process – Very thin oxide (EOT<1 nm) – Low leakage (IG<10 A/cm2) – Low Dit (<1012 eV-1.cm-2 in top ~0.3 eV of bandgap) – Reliable

• Some notable work:

Al2O3 by ALD (Purdue) Wu, EDL 2009 Al2O3 /GGO on InGaAs by MBE/ALD (Tsinghua) Hong, MRS Bull 2009

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TaSiOx on InGaAs by ALD (Intel) Radosavljevic, IEDM 2009

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2009 Intel InGaAs MOSFET (scaled to VDD=0.5 V)

In0.7Ga0.3As Quantum-Well MOSFET

Lg=75 nm InGaAs MOSFET outperforms state-or-the-art Si NMOS at 0.5 V Radosavljevic, IEDM 2009

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Critical problem: Mobility degradation in scaled gate stacks

• μ advantage over Si erodes away in thin barrier structures
• Remote Coulomb scattering at oxide/semiconductor interface

Graph courtesy of Prashant Majhi (Sematech) surface channel buried channel Si reference

Self-aligned device architecture

• The challenge:

– MOSFET structures with scalability to 10 nm – Self-aligned gate design

• Some notable work:

Ion-implanted self-aligned InGaAs MOSFET (NUS) Lin, IEDM 2008 Regrown ohmic contact MOSFET (NUS) Chin, EDL 2009 Quantum-well FET with self- aligned Mo contacts (MIT) Kim, IEDM 2010

G In0.53Ga0.47As InP In0.4Ga0.6As In-situ Doped S/D for RS Reduction

x y

Channel Strain Engineering for Mobility Enhancement

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60 nm

100 nm

Critical problem: contact scaling

Current contacts to III-V FETs are >100X off in required contact resistance

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Waldron, TED 2010 Reduce contact resistivity + resistance of contact stack

Today: ~200 ohm.μm Need: ~50 ohm.μm

P-channel MOSFETs

• The challenge:

– Performance >1/3 that of n-MOSFETs – Capable of scaling to <10 nm gate length regime – Co-integration with III-V NMOSFET on Si

• Some notable work:

Al2O3/InGaSb QW- MOSFET (Stanford) Nainani, IEDM 2010 Ga2O3/AlGaAs/GaAs MOSFET (Motorola) Passlack, EDL 2002 Al2O3 by ALD on InGaAs and Ge MOSFETs (IMEC) Lin, IEDM 2009

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How will a future 10 nm-class III-V MOSFET look like?

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• Quantum well + raised source/drain + self-aligned gate
• Two designs:

Recessed gate Regrown source and drain

• QW extends under S/D

 high μ preserved

• Critical interface protected until

late in process

• More freedom for S/D region

design

• Uniaxial strain possible

Critical problem: planar FET might not meet electrostatics requirements

• Electrostatic integrity might demand 3D III-V MOSFET

structures

• Some notable work:

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InAs Vertical Nanowire FETs (Lund) Egard, NanoLett 2010 InAs Nanowire FETs (UC Berkeley) Chueh, NanoLett 2008

p+ InP Fin-Channel Fin-Channel

Drain Source

p InP

EXT.

Gate

Fin-channel p+ InP Fin-Channel Fin-Channel Fin-Channel Fin-Channel

Drain Source

p InP

EXT.

Gate

Fin-channel

InGaAs FinFET (Purdue, Intel) Wu, IEDM 2009 Radosavljevic, IEDM 2010

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Conclusions

• III-Vs attractive for CMOS: key for low VDD operation

– Electron injection velocity > 2X that of Si at 1/2X VDD – Quantum-well channel yields outstanding short-channel effects

• Impressive recent progress on III-V CMOS

– Ex-situ ALD and MOCVD on InGaAs yield interfaces with unpinned Fermi level and low defect density – Sub-100 nm InGaAs MOSFETs with ION > than Si at 0.5 V demonstrated

• Lots of work ahead

– Demonstrate 10 nm III-V N-MOSFET that is better than Si – P-channel MOSFET – N-channel + P-channel cointegration