Calibration of a FPGA TDC M. Heil GSI Helmholtzzentrum fr - - PowerPoint PPT Presentation

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calibration of a fpga tdc
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Calibration of a FPGA TDC M. Heil GSI Helmholtzzentrum fr - - PowerPoint PPT Presentation

Feb 17, 2024 282 likes •401 views

GSI Helmholtzzentrum fr Schwerionenforschung GmbH Calibration of a FPGA TDC M. Heil GSI Helmholtzzentrum fr Schwerionenforschung GmbH Time-over-Threshold measurements signal signal threshold integrated signal threshold ToT leading

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GSI Helmholtzzentrum für Schwerionenforschung GmbH GSI Helmholtzzentrum für Schwerionenforschung GmbH

Calibration of a FPGA TDC

  • M. Heil
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GSI Helmholtzzentrum für Schwerionenforschung GmbH

Time-over-Threshold measurements

threshold ToT leading edge trailing edge ToT=tle -tte Conversion from an amplitude or charge measurement to a time measurement. threshold ToT leading edge trailing edge signal integrated signal signal

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GSI Helmholtzzentrum für Schwerionenforschung GmbH

Working principle of a “normal” TDC

  • Time is measured between start and stop signal.
  • Each bin has same time duration.
  • Time measurement is limited to a certain number of channels.
  • Calibration with a time calibrator.

Δt individual stop

50 100 150 200 250 20 40 60 80 100 Time in ns Channels

common start

calibration with slope

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GSI Helmholtzzentrum für Schwerionenforschung GmbH

Working principle of a FPGA TDC

  • Time measurement split in coarse (clock cycle) and fine (channel) time.

signal clock

fine time coarse time

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GSI Helmholtzzentrum für Schwerionenforschung GmbH

Working principle of a FPGA TDC

  • Time measurement split in coarse (clock cycle) and fine (channel) time.
  • LVDS Signal is sampled via delays of carry chain of FPGA.
  • Signal level is recorded in logic modules (flip flops)

signal clock

fine time coarse time

Delays are not constant !!! Every channel has a different bin size. Results are stored in a buffer and can be read out later by a read-out trigger.

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GSI Helmholtzzentrum für Schwerionenforschung GmbH

Calibration of times

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GSI Helmholtzzentrum für Schwerionenforschung GmbH

Calibration of times

t_ns=clockCycle*clockTime - fineTime running sum of bins 𝑔𝑗𝑜𝑓𝑈𝑗𝑛𝑓 𝑐𝑗𝑜 = 𝑑𝑝𝑣𝑜𝑢𝑡(𝑗)

𝑗=𝑐𝑗𝑜 𝑗=0

𝑑𝑝𝑣𝑜𝑢𝑡(𝑗)

𝑗=𝑛𝑏𝑦 𝑗=0

clockTime Calibration done channel by channel as look-up table

channel time in ns

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GSI Helmholtzzentrum für Schwerionenforschung GmbH

Overflow of coarse counter

  • The coarse counter of Tamex2 (Ptof) is reset at 8191. Time

differences for which one coarse counter is reset have peculiar

  • times. This has to be corrected.

e.g.: while(tt-tl<0){ tt=tt+2048*clockTime; }

  • The coarse counter of VFTX2 (LOS) is reset at 2047. Time

differences between LOS and Ptof have to be corrected for this.

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GSI Helmholtzzentrum für Schwerionenforschung GmbH

Time-of-flight measurements in Cave C

  • All times are measured relative to one common clock signal.

PToF

clock distribution

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GSI Helmholtzzentrum für Schwerionenforschung GmbH

Pictures of setup and FPGA TDCs

VFTX2 TAMEX3 TAMEX2 ToF wall

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GSI Helmholtzzentrum für Schwerionenforschung GmbH

Advantages of FPGA TDC

  • Long time differences can be measured accurately by dividing the time

into a coarse and fine measurement.

  • FPGA TDC measures time differences with a precision of up to σt~7 ps.
  • It can be calibrated with physics data. No time calibrator necessary.
  • All events within a large trigger window of ±10 µs can be stored and

read out later by a read-out trigger.

  • It can handle multi-hits.
  • All detectors measure relative to same clock signal.