FPGA high-resolution TDC Development of high-resolution TDC based - - PowerPoint PPT Presentation

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FPGA high-resolution TDC Development of high-resolution TDC based on FPGA. , A , JAEA B , KEK C , Open-It D @ , A , B , CD , CD SNP

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FPGAを用いた high-resolution TDCの開発 Development of high-resolution TDC based on FPGA.

阪大理, 東北大理A, JAEAB, KEKC, Open-ItD @本多良太郎, 三輪浩司A, 細見健二B, 池野正弘CD, 内田智久CD

SNPスクール2017＠福島

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Outline

SNPスクール2017＠福島

  • Motivation
  • Developed items
  • Hardware
  • Tapped delay line in FPGA
  • Calibration
  • Performance evaluation
  • Summary
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Motivation

SNPスクール2017＠福島

Background proton are rejected by 2nd level trigger triggered by 2nd level

Mass-square distribution of scattered particles.

triggered by 1st level

Target Beam spectrometer

Beam p

Analyzer magnet TOF

Aerogel Cherenkov (AC) Lucite Cherenkov (LC)

K+ p+ p

Backgrounds

  • 1st level trigger : Coincidence of detector signals
  • Cherenkov detectors play important role.
  • 2nd level trigger : Trigger based on time-of-flight
  • High-resolution time-of-flight information is

necessary.

Timing reference

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Motivation

SNPスクール2017＠福島 TFC (4303) FERA (4300) FERA driver FPGA trigger module

LC TOF VME CAMMAC

Present 2nd level trigger system New trigger system

FPGA FPGA

FPGA based high-resolution TDC mezzanine card Trigger controller module (Mother module)

  • Slow (10 μs order)
  • Complex
  • Old
  • Fast (100 ns order)
  • Simple

Supported by Grant 新学術 (中性子星核物質) 公募研究 「J-PARC二次ビーム高強度化のための汎用トリガーモジュールの開発」

Development of FPGA based HR-TDC is main motivation of this project.

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Motivation

SNPスクール2017＠福島 TFC (4303) FERA (4300) FERA driver FPGA trigger module

LC TOF VME CAMMAC

Present 2nd level trigger system New trigger system

FPGA FPGA

FPGA based high-resolution TDC mezzanine card Trigger controller module (Mother module)

Supported by Grant 新学術 (中性子星核物質) 公募研究 「J-PARC二次ビーム高強度化のための汎用トリガーモジュールの開発」

Development of FPGA based HR-TDC is main motivation of this project.

  • Slow (10 μs order)
  • Complex
  • Old
  • Fast (100 ns order)
  • Simple

In general, the common issue in our research field is that no GOOD common-stop type high-resolution TDC exists. We must overcome this problem for future experiments.

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Developed hardware

SNPスクール2017＠福島

Hadron universal logic (HUL) controller module

  • 64ch ECL/LVDS inputs
  • Two mezzanine slots
  • GbE : SiTCP (VME communication is not supported)
  • Powered by J1 or AC adaptor (5V)

HUL mezzanine cards

This project is technically supported by Open-It.

http://openit.kek.jp/project/HUL/public/hul

Today’s topic is implementation of HR-TDC into Xilinx Kintex7 160T on HUL controller.

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Principle of Tapped Delay Line HR-TDC

SNPスクール2017＠福島

Tapped Delay Line (TDL)

Sampling clock Hit Deley D-FF

Pulse runs on TDL

D-Flip-Flop captures the snapshot of the pulse running on TDL.

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Implementation of TDL into FPGA

FPGA : Field-Programmable Gate Array

  • Gate level logic coded by users can be implemented.

Implement TDL using carry line in FPGA Carry line

  • Basic function of Adder
  • Smallest delay element with 5-30 ps delay time
  • Close to FF
  • Cascadable

Xilinx UG474

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Implemented logic

Tapped delay line Remapping (192 → 64 taps) Leading edge finder Binary encoder Crock domain crossing Calibration table Ring buffer (15.8 us length) 520 MHz 130 MHz 11111111111111000000000000000 Pulse run 1111100000 0000100000 5 Event build process 32ch HR-Timing unit and DAQ functions were fully implemented into Kintex7 160T. : Fine count + Semi coarse count (2bit) + Coarse count (11bit)

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Distribution of delay time

Sampling clock

Hit

D-FF

dT1 dT2 dT3 dT4 dT5

Delay time (dT) is not constant. Tap number histogram

Period of sampling clock 1.92 ns

dT distribution for all the channels dT = Count/TotalEntry*1920 ps

Most probable dT is 30 ps

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Calibration of TDL

RAM Tap number (RAM address) Calibrated data (RAM data) Switch LUT table if the other is ready. +1 at addressed register Accumulate 0x7ffff events, and after that, create new table. RAM

Tap number histogram Calibrated look up table

Nth Val = wn/2 + Σn-1

0 (wi)

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  • Use detector signal.
  • Corresponding to that the clock sampling of the detector signal. The detector

signal must be random.

  • Use clock.
  • The TDC clock is 520 MHz (fsample) and calibration clock is 26.2144 (fcalib)
  • N*(fsample/fcalib) = N*(29*57*13)/(220*52) = N*(55*13)/211
  • 2048 different clock phases appear

Calibration of method

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DAQ functions

Event packet Event packet SiTCP

Discard event if clear was received.

Event packet TDC unit Ring buffer Ch buffer Input TDC unit Ring buffe Ch buffer Input TDC unit

Ring buffer

Input x 32ch TDC block HR-Multi-Hit TDC Build an Event

Channel buffer

TDC data TDC data L2 data L2 data

  • L2 trigger
  • Clear
  • Tag

Trigger module Trigger information

Data transmit if L2 was received.

Block buffer Event buffer

Channel : 32 Trigger type : Common stop Ring buffer length : 15.8 us MaxHit/ch/event : 16 Dead time : Equal to search window Ring buffer

Hits inside the search window are stored in channel buffer, when trigger is received.

TDC unit Common stop

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Performance evaluation

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Timing resolution

Timing resolution between each channel and common stop Timing distribution between ch1 and common stop

Timing resolution better than 30 ps (s) achieved for all the channel !

Discriminator

Random pulse

HUL (HR-TDC) NIM/LVDS start 10 ns delay

common stop

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Double hit resolution

5ns 4ns 4ns

Input pulse

Measured timing distribution

Double pulse could be measured with 100% efficiency. 8 ns

2ns 2ns

In principle, double pulses with quite short interval can be measured .

2ns

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Double hit resolution

5ns 4ns 4ns

Input pulse

Measured timing distribution

8 ns Double pulse could be measured with 100% efficiency.

2ns 2ns

In principle, double pulses with quite short interval can be measured .

2ns

High-resolution multi-hit TDC was successfully developed. We overcame HR-TDC problem in our field !

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ToDo

Implement both leading and trailing edges measurement.

  • At present, 8ch leading/trailing measurement was achieved.

Implement HR-TDC to FPGA on mezzanine card.

  • Separate HR-TDC part from the DAQ functions.
  • Customization of DAQ functions can be easy.

New mezzanine card for HR-TDC (Same FPGA is mounted)

Future possibility

  • Synchronization with master clock
  • Implement as free-run type TDC
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Summary

  • Develop the 2nd level trigger system using FPGA based HR-TDC for the K+ selection in

J-PARC experiments.

  • Furthermore, FPGA based HR-TDC solve the problem that no good HR-TDC exists in
  • ur research field.
  • Tapped delay line HR-TDC, which realized by carry line, was implemented into Xilinx

Kintex7 160T.

  • 32ch HR-TDC unit and DAQ functions were fully implemented.
  • The timing resolution better than 30 ps (s) was achieved for all the channel.
  • The double-hit resolution was at least 8 ns.
  • We overcame the HR-TDC problem by this development.
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Backup

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Principle of calibration using clock.

clip at every 1.92 ns Projection to Y

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LUT Entry dependence of timing resolution

Timing resolution of ch0-ch1 (NIM) Timing resolution of ch2-ch3 (ECL) At present, LUT table accumulate 0x7ffff events. Present setting

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Bit length dependence of timing resolution

Timing resolution of ch0-ch1 (NIM) Timing resolution of ch2-ch3 (ECL) At present, lower 8bits are discarded.