GRVI Phalanx Update: A Massively Parallel RISC-V FPGA Accelerator - - PowerPoint PPT Presentation

▶
grvi phalanx update
SMART_READER_LITE
LIVE PREVIEW

GRVI Phalanx Update: A Massively Parallel RISC-V FPGA Accelerator - - PowerPoint PPT Presentation

Dec 07, 2023 214 likes •512 views

GRVI Phalanx Update: A Massively Parallel RISC-V FPGA Accelerator Framework Jan Gray | jan@fpga.org | http://fpga.org CARRV2017: 2017/10/14 FPGA Datacenter Accelerators Are Almost Mainstream Catapult v2. Intel += Altera. OpenPOWER CAPI. AWS

slide-1
SLIDE 1

GRVI Phalanx Update:

A Massively Parallel RISC-V FPGA Accelerator Framework Jan Gray | jan@fpga.org | http://fpga.org

CARRV2017: 2017/10/14

slide-2
SLIDE 2

FPGA Datacenter Accelerators Are Almost Mainstream

  • Catapult v2. Intel += Altera. OpenPOWER CAPI.

AWS F1. Baidu. Alibaba. Huawei …

  • FPGAs as computers

– Massively parallel, customized, connected, versatile – High throughput, low latency, low energy

  • Great, except for two challenges

– Software: C++ workload  ???  FPGA accelerator? – Hardware: “tape out” a complex SoC daily?

2 CARRV2017: 2017/10/14

slide-3
SLIDE 3

Hardware Challenge

NIC 1 NIC 2 NIC 3 NIC 4 HBM CHANNEL 1

FPGA

HBM CHANNEL 2 DRAM CHANNEL 1 DRAM CHANNEL 2

PHY PHY PHY PHY

10G…100G NETWORKS

HBM HIGH BANDWIDTH MEMORY

. . . . . .

HOST PERIPH

PCI EXPRESS 1 PCI EXPRESS 2

A1 A1 A1 A1 A1 A1 A1 A1 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2

ACCELERATORS

3 CARRV2017: 2017/10/14

slide-4
SLIDE 4

GRVI Phalanx: FPGA Accelerator Framework

  • For software-first accelerators:

– Run parallel software on 100s of soft processors – Add custom logic as needed = More 5 second recompiles, fewer 5 hour PARs

  • GRVI: FPGA-efficient RISC-V RV32I soft CPU
  • Phalanx: processor/accelerator fabric

– Many clusters of PEs, RAMs, accelerators, I/O – Message passing in a PGAS across a …

  • Hoplite NoC: FPGA-optimal fast/wide 2D torus

4 CARRV2017: 2017/10/14

slide-5
SLIDE 5

Why RISC-V?

  • Open ISA, welcomes innovation
  • Comprehensive infrastructure and ecosystem

– Specs, tests, simulators, cores, compilers, libs, FOSS

  • As with LLVM, research will accrue to RISC-V
  • Its simple ISA allows an efficient FPGA soft CPU

CARRV2017: 2017/10/14 5

slide-6
SLIDE 6

GRVI: Austere RISC-V Processing Element

  • Simpler, smaller processors  more processors

 more task and memory parallelism

  • GRVI core

– RV32I, minus CSRs, exceptions, plus mul*, lr/sc – 3 stage pipeline (fetch, decode, execute) – 2 cycle loads; 3 cycle taken branches/jumps – Typically 320 LUTs @ 375 MHz ≈ 0.7 MIPS/LUT

CARRV2017: 2017/10/14 6

slide-7
SLIDE 7

GRVI RV32I Microarchitecture

CARRV2017: 2017/10/14 7

slide-8
SLIDE 8

GRVI RV32I Datapath: ~250 LUTs

8 CARRV2017: 2017/10/14

slide-9
SLIDE 9

GRVI Cluster:

0-8 PEs + 32-256 KB Shared Memory

CARRV2017: 2017/10/14 9

P P P P P P P P 2:1 2:1 2:1 2:1 4:4

XBAR

CMEM = 128 KB CLUSTER DATA IMEM 4-8 KB ACCELERATOR(S) 64 IMEM 4-8 KB IMEM 4-8 KB IMEM 4-8 KB

slide-10
SLIDE 10

10 CARRV2017: 2017/10/14

GRVI Cluster Tile: ~3500 LUTs

slide-11
SLIDE 11

Composing Clusters with Message Passing

  • n a Hoplite NoC
  • Hoplite: rethink FPGA NoC router architecture

– No segmentation/flits, VCs, buffering, credits – Unidirectional rings – Deflecting dimension order routing of whole msgs – Simple; frugal; wide; fast: 1-400 Gbps/link

  • 1% area×delay of FPGA-tuned VC flit routers

11 CARRV2017: 2017/10/14

slide-12
SLIDE 12

Example Hoplite NoC

12 CARRV2017: 2017/10/14

256b links @ 400 MHz = 100 Gb/s links; <3% of FPGA

slide-13
SLIDE 13

GRVI Cluster with NoC Interfaces

CARRV2017: 2017/10/14 CARRV2017: 2017/10/14

P P P P P P P P 2:1 2:1 2:1 2:1 4:4

XBAR

CMEM = 128 KB CLUSTER DATA IMEM 4-8 KB NoC ITF ACCELERATOR(S)

HOPLITE ROUTER

64 IMEM 4-8 KB IMEM 4-8 KB IMEM 4-8 KB 300 = header + 32b msg dest addr + 256b msg data

slide-14
SLIDE 14

10×5 Clusters × 8 GRVI PEs = 400 GRVI Phalanx (KU040, 12/2015)

14 CARRV2017: 2017/10/14

slide-15
SLIDE 15

Parallel Programming Models?

  • Small kernels, local or PGAS shared memory,

message passing, memcpy/RDMA DRAM

  • Current: multithreaded C++ w/ message passing

– Uses GCC for RISC-V RV32IMA. Thank you!

  • Future: OpenCL, KPNs, P4, …

– Accelerated with custom FUs, AXI cores, RAMs

CARRV2017: 2017/10/14 15

slide-16
SLIDE 16

11/30/16: Amazon AWS EC2 F1!

CARRV2017: 2017/10/14 16

slide-17
SLIDE 17

F1’s UltraScale+ XCVU9P FPGAs

  • 1.2 M 6-LUTs
  • 2160 36 Kb BRAMs (8 MB)
  • 960 288 Kb URAMs (30 MB)
  • 6840 DSPs

CARRV2017: 2017/10/14 17

slide-18
SLIDE 18

1680 RISC-Vs, 26 MB CMEM (VU9P, 12/2016)

  • 30×7 clusters of { 8 GRVI, 128 KB CMEM, router }
  • First kilocore RISC-V, and the most 32b RISC

cores on a chip in any technology

CARRV2017: 2017/10/14 18

slide-19
SLIDE 19

1, 32, 1680 RISC-Vs

CARRV2017: 2017/10/14 19

slide-20
SLIDE 20

1680 Core GRVI Phalanx Statistics

CARRV2017: 2017/10/14 20

Resource Use

  • Util. %

Logical nets 3.2 M

  • Routable nets

1.8 M

  • CLB LUTs

795 K 67.2% CLB registers 744 K 31.5% BRAM 840 38.9% URAM 840 87.5% DSP 840 12.3%

Frequency 250 MHz Peak MIPS 420 GIPS CRAM Bandwidth 2.5 TB/s NoC Bisection BW 900 Gb/s Power (INA226) 31-40 W Power/Core 18-24 mW/core MAX VCU118 Temp 44C Vivado 2016.4 / ES1 Max RAM use ~32 GB Flat build time 11 hours Tools bugs

>1000 BRAMs + 6000 DSPs available for accelerators

slide-21
SLIDE 21

XEON

Amazon F1.2xlarge Instance

CARRV2017: 2017/10/14 21

XEON VU9P DRAM ENA NVMe DRAM 64 GB 122 GB

slide-22
SLIDE 22

XEON

Amazon F1.16xlarge Instance

CARRV2017: 2017/10/14 22

DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM DRAM XEON VU9P VU9P VU9P VU9P VU9P VU9P VU9P VU9P ENA PCIe SWITCH FABRIC 64 GB 976 GB NVMe NVMe NVMe NVMe

slide-23
SLIDE 23

Recent Work

  • Bridge Phalanx and AXI4 system interfaces

– Message passing with host CPUs (x86 or ARM) – DRAM channel RDMA request/response messaging

  • “SDK” hardware targets

– 1000-core AWS F1 (<$2/hr) – 80-core PYNQ (Z7020) ($65 edu)

CARRV2017: 2017/10/14 23

slide-24
SLIDE 24

GRVI Phalanx on Zynq with AXI Bridges

CARRV2017: 2017/10/14 24

slide-25
SLIDE 25

PYNQ-Z1 Demo: Parallel Burst DRAM Readback Test: 80 Cores × 228 × 256 B

CARRV2017: 2017/10/14 25

slide-26
SLIDE 26

1240 1240 1240 1240 1240 1240 1240

GRVI Phalanx on AWS F1 (WIP)

CARRV2017: 2017/10/14 26

900 9920

(Not yet bridged; F1.16XL)

1240

slide-27
SLIDE 27

4Q17 Work in Progress

  • Complete initial F1.2XL and F1.16XL ports
  • GRVI Phalanx SDK

– Specs, libraries, examples, tests – As PYNQ Jupyter Python notebooks, bitstreams – AMI+AFI in AWS Marketplace

  • Full instrumentation – event counters; tracing
  • Evaluate porting effort & perf on workloads TBD

CARRV2017: 2017/10/14 27

slide-28
SLIDE 28

In Conclusion

  • Enable programmers to access massive

reconfigurable / memory parallelism

  • Frugal design enables competitive performance
  • Value proposition unproven, awaits workloads
  • SDK coming soon, enabling parallel RISC-V

research and teaching on 80-8,000 core systems

CARRV2017: 2017/10/14 28

Thank you