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Slides for Lecture 32
ENEL 353: Digital Circuits — Fall 2013 Term Steve Norman, PhD, PEng
Electrical & Computer Engineering Schulich School of Engineering University of Calgary
Slides for Lecture 32 ENEL 353: Digital Circuits Fall 2013 Term - - PowerPoint PPT Presentation
Slides for Lecture 32 ENEL 353: Digital Circuits Fall 2013 Term - - PowerPoint PPT Presentation
Slides for Lecture 32 ENEL 353: Digital Circuits Fall 2013 Term Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary 25 November, 2013 slide 2/19 ENEL 353 F13 Section 02
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ENEL 353 F13 Section 02 Slides for Lecture 32
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Today’s Lecture
Completion of a timing analysis example. Introduction to clock skew. Adjustment of setup and hold time constraint inequalities to account for clock skew. What can happen when setup and hold time constraints are violated? Introduction to metastability. Related reading in Harris & Harris: Sections 3.5.2–3.5.4
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ENEL 353 F13 Section 02 Slides for Lecture 32
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Completion of a timing analysis example
Available inverters have tcd = 9 ns and tpd = 15 ns. DFF timing parameters, in ns, are given in the table.
FooLogic BarTron CLK Y
family parameter Foo Bar tsetup 2 20 thold 1 7 tpcq 8 50 tccq 5 30 A student tests the circuit with a 1 MHz CLK input, expecting to see a 250 kHz square wave on Y. The circuit doesn’t work because of a hold time violation at the BarTron DFF input. What can be done to fix the circuit?
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Solutions for the hold time violation
Solution 1: Add delay on the path from the Foo
- utput to the Bar input.
CLK Y FooLogic BarTron
Solution 2: Switch the two flip-flops. One inverter provides enough delay.
BarTron FooLogic CLK Y
DIY (Do It Yourself): Check that there are no hold-time violations in either of the above circuits. Remark: It is generally a bad idea to combine flip-flops with very different timing parameters in a single synchronous design!
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Introduction to clock skew
This list is review. It’s a list of sufficient conditions for building a synchronous sequential circuit . . .
- 1. Every element in the circuit either is a register or is
combinational.
- 2. At least one element is a register.
- 3. All registers receive the same clock signal.
- 4. Every cyclic path in the circuit passes through at least
- ne register.
Unfortunately, the laws of physics make it very hard to perfectly satisfy condition 3 . . .
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Introduction to clock skew, continued
It takes time for a voltage change to propagate along a wire.
clock source
R1 Q1 D1 R2 Q2 D2 R3 Q3 D3 CLK1 CLK2 CLK3 Clock edges received by R1 are early relative to clock edges received by R2. Clock edges received by R3 are late relative to clock edges received by R2.
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Minimization of clock skew; definition of tskew
Clock skew is the name given to the problem having having different registers get clock edges at slightly different names. Delay from the clock source to clock inputs cannot be
- avoided. Circuit designers try to minimize clock skew by
making all the source-to-input delays very close to the
- same. (Because delays can be affected by factors such as
electrical noise, clock skew can’t be made zero just by making all clock-source-to-clock-input wires the same length.) In a synchronous sequential circuit, tskew is defined as the worst-case difference in times of arrival of an active clock edge at any two registers in the circuit.
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Clock skew, setup and hold time constraints
CLK1 and CLK2 come from the same clock source, but due to clock skew, clock edges might not arrive at R1 and R2 at exactly the same time. C L Q1 D1 Q2 D2 R1 R2 CLK1 CLK2 Review: If it happens that that there is no clock skew, then we know for safe operation this must be true . . . tpd for C L ≤ TC − (tpcq + tsetup) (tsetup constraint) tcd for C L ≥ thold − tccq (thold constraint)
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Clock skew and the setup time constraint
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C L Q1 D1 Q2 D2 R1 R2 CLK1 CLK2 Suppose CLK2 is early relative to CLK1. For reliable
- peration, what must be true about the speed of the
combinational logic? (The gold rectangle shows the tsetup/thold aperture for R2.) CLK1 CLK2 D2 Q1 tpcq tpd tskew
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Clock skew and the hold time constraint
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C L Q1 D1 Q2 D2 R1 R2 CLK1 CLK2 Now suppose CLK2 is late relative to CLK1. For reliable
- peration, what must be true about the speed of the
combinational logic? (Again, the gold rectangle shows the tsetup/thold aperture for R2.) CLK1 CLK2 D2 Q1 tskew tccq tcd
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Summary of timing constraints in the presence of clock skew
setup time constraint: tpd ≤ TC − (tpcq + tsetup + tskew) hold time constraint: tcd ≥ thold + tskew − tccq Things to note:
◮ If we set tskew = 0, we get the same inequalities we
derived in the previous lecture.
◮ Both inequalities say that as tskew increases, the designer’s
job gets more difficult. tpd may need to be reduced on some paths, and tcd may need to be increased on other paths.
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Review of a simple timing example
Here there is a violation of the setup-and-hold-time rules around t1. CLK D Q
t0 t1
? ? ? What happens to Q after t1? There are multiple possibilities. Let’s look at these multiple possibilities in more detail.
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An odd-looking example circuit
Connecting one signal to four register inputs will let us make a point about the variety of possible responses to an aperture time violation. Q3 Q2 Q1 Q0 D
CLK
The DFFs in the register are very close to identical, but not perfectly so, due to minor manufacturing variations. If the setup and hold time rules are respected, all four Q values will copy D on each rising edge of CLK, with a delay in the range from tccq to tpcq. What might happen if the setup and hold time rules are violated?
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Example responses to a setup time violation
Here we assume that Q3:0 = 0000 before the rising edge of CLK.
CLK
D Q0 Q1 Q2 Q3
Let’s make some remarks about these responses.
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Metastability in latches and flip-flops
In normal operation the Q and Q signals of a latch or flip-flop will sit in one or the other of two stable states: (Q, Q) = (0, 1) or (Q, Q) = (1, 0). Metastability is the name given to a kind of abnormal behaviour in which the voltages of the Q and Q signals both sit approximately halfway between 0 and VDD for some period of time called tres, the resolution time. Once the resolution time has passed, the latch or flip-flop goes to (“resolves” to) one or the other of its stable states. tres is random, differing in length from one instance of metastability to the next.
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A mechanical analogy for metastability
There are two stable places for the ball: the bottom of valley 0, and the bottom of valley 1. hill valley 1 valley 0 Given a gentle nudge, the ball will move a little, but stay in valley 0. Given a strong push, the ball will roll over the hill and settle in valley 1. What if the ball is given a push that gives it just enough energy to get to the top of the hill and stop?
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Why is metastability dangerous?
The key problem is this: tres will sometimes be much longer than tpcq. Sometimes tres may be as long as one whole clock period in a synchronous system. Of course, the output signal of a flip-flop or latch is typically an input signal to one or more other circuit elements. A circuit element with a metastable input will probably generate an incorrect output. So metastability in a single DFF could cause an entire synchronous circuit to behave incorrectly, possibly getting the circuit into a state from which it can’t recover.
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