Towards Sub-10 nm Diameter I nGaAs Vertical Nanowire MOSFETs and - - PowerPoint PPT Presentation

Towards Sub-10 nm Diameter I nGaAs Vertical Nanowire MOSFETs and TFETs

• J. A. del Alamo, X. Zhao, W. Lu, and A. Vardi

Microsystems Technology Laboratories

Massachusetts Institute of Technology

5th Berkeley Symposium on Energy Efficient Electronic Systems & Steep Transistors Workshop Berkeley, CA, October 19-20, 2017 Acknowledgements:

• Students and collaborators: D. Antoniadis, E. Fitzgerald, E. Yablonovitch
• Sponsors: DTRA, KIST, Lam Research, Samsung, SRC
• Labs at MIT: MTL, EBL

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Vertical Nanowire MOSFETs: the ultimate scalable transistor

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Vertical nanowire MOSFET: ultimate scalable transistor

Vertical NW MOSFET:  uncouples footprint scaling from Lg, Lspacer, and Lc scaling Lc Lg Lspacer

I nGaAs Vertical Nanowires on Si by direct growth

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Selective-Area Epitaxy (SAE) Au seed Vapor-Solid-Liquid (VLS) Technique InAs NWs on Si by SAE Riel, MRS Bull 2014 Riel, IEDM 2012

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I nGaAs VNW-MOSFETs by top-down approach @ MI T

Top-down approach: flexible and manufacturable

n+ InGaAs, 70 nm i InGaAs, 80 nm n+ InGaAs, 300 nm

Starting heterostructure: n+: 6×1019 cm-3 Si doping

Key enabling technologies:

• RIE = BCl3/SiCl4/Ar chemistry
• Digital Etch (DE) =

self-limiting O2 plasma oxidation + H2SO4 or HCl oxide removal

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• Radial etch rate=1 nm/cycle
• Sub-20 nm NW diameter
• Aspect ratio > 10
• Smooth sidewalls

RIE + 5 cycles DE

Zhao, IEDM 2013 Zhao, EDL 2014 Zhao, IEDM 2014

I nGaAs Vertical Nanowires @ MI T

I I I -V VNW MOSFET/ TFET process flow

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NW-MOSFET I -V characteristics: D= 40 nm

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Single nanowire MOSFET:

• Lch= 80 nm
• 3 nm Al2O3 (EOT = 1.5 nm)
• 0.2

0.0 0.2 0.4 0.6 10

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Vds=0.5 V

Vgs(V) Is (A/µm)

Vds=0.05 V

0.0 0.1 0.2 0.3 0.4 0.5 50 100 150 200 250 300

Vgs=-0.2 V to 0.7 V in 0.1 V step

Vds (V)

Is (µA/µm)

• 0.2

0.0 0.2 0.4 0.6 100 200 300 400 500 600 700 800 Vgs(V) gm (µS/µm) Vd= 0.5 V

gm,pk=720 μS/μm

Slin = 70 mV/dec Ssat = 80 mV/dec DIBL = 88 mV/V

Zhao, CSW 2017

Benchmark with Si/ Ge VNW MOSFETs

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• InGaAs competitive with Si
• Need to demonstrate VNW MOSFETs with D<10 nm

20 40 60 80 100 200 400 600 800 1000 1200 1400 1V 1 V

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1 V 1.2 V 1.2 V

gm,pk (µS/µm) Si/Ge InGaAs Diameter (nm)

Peak gm of InGaAs (VDS=0.5 V), Si and Ge VNW MOSFETs

Target

Our work (VDS=0.5 V)

I nGaAs VNW Mechanical Stability for D< 10 nm

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8 nm InGaAs VNWs: Yield = 0%

Broken NW

Difficult to reach 10 nm VNW diameter due to breakage 8 nm InGaAs VNWs after 7 DE cycles:

I nGaAs VNW Mechanical Stability for D< 10 nm

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8 nm InGaAs VNWs: Yield = 0%

Broken NW

Difficult to reach 10 nm VNW diameter due to breakage Water-based acid is problem:

Surface tension (mN/m):

• Water: 72
• Methanol: 22
• IPA: 23

Solution: alcohol-based digital etch

Alcohol-Based Digital Etch

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10% HCl in IPA Yield = 97% 10% HCl in DI water Yield = 0%

Alcohol-based DE enables D < 10 nm

Broken NW

Radial etch rate: 1.0 nm/cycle Radial etch rate: 1.0 nm/cycle

8 nm InGaAs VNWs after 7 DE cycles: Lu, EDL 2017

D= 5.5 nm VNW arrays

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90% yield

10% H2SO4 in methanol

• H2SO4:methanol yields 90% at D=6 nm!
• Viscosity matters: methanol (0.54 cP) vs. IPA (2.0 cP)

I nGaAs Digital Etch

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First demonstration of D=5 nm diameter InGaAs VNW (Aspect Ratio > 40)

15 0.0 0.1 0.2 0.3 0.4 0.5 50 100 150 200 Vgs= 0 V to 0.6 V in 0.1 V step

Ron= 5500 Ω⋅µm

Mo contact D = 15 nm 300

• C N2 RTA

Vds (V)

Id (µA/µm)

Latest! D= 15 nm I nGaAs VNW MOSFET

Single nanowire MOSFET:

• Lch= 80 nm
• 2.5 nm Al2O3 (EOT = 1.3 nm)

Zhao, IEDM 2017

Benchmark with Si/ Ge VNW MOSFETs

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Most aggressively scaled VNW MOSFET ever Peak gm of InGaAs (VDS=0.5 V), Si and Ge VNW MOSFETs

Target

Our latest work (VDS=0.5 V)

Even better results at IEDM 2017!

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I nGaAs/ I nAs heterojunction VNW TFETs @ MI T

Top-down approach: flexible and manufacturable

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Gen-2 I nGaAs VNW-TFET

0.0 0.1 0.2 0.3 0.4 0.5 0.0 0.5 1.0 1.5 2.0

Vgs=0 V to 0.6 V in 0.1 V step Vds (V)

Id (µA/µm)

• 0.4
• 0.2

0.0 0.2 0.4 10

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Vgs= 0 V to 0.6 V in 0.1 V step Vds (V)

Id (µA/µm)

• Saturated output characteristics
• Clear negative differential resistance
• Peak to valley ratio of 3.4 @ Vgs = 0.6 V

Zhao, EDL 2017 Single NW: D= 40 nm, Lch= 60 nm, 3 nm Al2O3 (EOT = 1.5 nm) New step: final RTA→ 10 fold reduction in Dit

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NW-TFET subthreshold characteristics

0.0 0.1 0.2 0.3 0.4 0.5 10

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Vd=0.3 V Vgs(V) Id (A/µm) Vd=0.05 V

• Sub-thermal for 2 orders of magnitude of current
• Slin = 55 mV/dec
• Ssat = 53 mV/dec

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S (mV/dec) Id (A/µm)

Vd = 0.05 V Vd = 0.3 V

T=300 K

Zhao, EDL 2017

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f [Hz] SId/I

2 d (Hz

• 1)

Welch 1/f2 1/f

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Random Telegraph noise (RTN) in TFETs

• RTN consistent with jump in subthreshold current
• Single-trap behavior visible

10 20 30 40 1n 1n 1n 2n 2n 2n 2n 2n 3n Vds = 50 mV Vgs = 0.24 V

Time [S] Id (A)

10 20 30 40 300p 400p 500p 600p 700p 800p 900p Vds = 50 mV Vgs = 0.18 V

Time [S] Id (A)

10 10

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f [Hz] SId/I

2 d (Hz

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Welch 1/f2 1/f 0.0 0.1 0.2 0.3 0.4 0.5 0.6 10

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Jump Slin = 61 mV/dec Ssat = 66 mV/dec Vds=0.3 V

Vgs(V) Id (A/µm)

Vds=0.05 V

Conclusions

• Improved InGaAs etching technology: sub-10 nm

nanowires with very high aspect ratio and high yield

• InGaAs VNW MOSFETs with record characteristics
• InGaAs VNW TFETs with subthermal behavior over 2
• rders of magnitude of ID
• Exciting new results to be presented at IEDM 2017

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