Towards Sub-10 nm Diameter I nGaAs Vertical Nanowire MOSFETs and TFETs J. A. del Alamo, X. Zhao, W. Lu, and A. Vardi Microsystems Technology Laboratories Massachusetts Institute of Technology 5 th Berkeley Symposium on Energy Efficient Electronic Systems & Steep Transistors Workshop Berkeley, CA, October 19-20, 2017 Acknowledgements: • Students and collaborators: D. Antoniadis, E. Fitzgerald, E. Yablonovitch • Sponsors: DTRA, KIST, Lam Research, Samsung, SRC • Labs at MIT: MTL, EBL
Vertical Nanowire MOSFETs: the ultimate scalable transistor 2
Vertical nanowire MOSFET: ultimate scalable transistor L c L spacer L g Vertical NW MOSFET: uncouples footprint scaling from L g , L spacer , and L c scaling 3
I nGaAs Vertical Nanowires on Si by direct growth Au seed InAs NWs on Si by SAE Riel, MRS Bull 2014 Vapor-Solid-Liquid Selective-Area Epitaxy (SAE) (VLS) Technique Riel, IEDM 2012 4
I nGaAs VNW-MOSFETs by top-down approach @ MI T Starting heterostructure: n + InGaAs, 70 nm i InGaAs, 80 nm n + InGaAs, 300 nm n + : 6 × 10 19 cm -3 Si doping Top-down approach: flexible and manufacturable 5
I nGaAs Vertical Nanowires @ MI T Key enabling technologies: • RIE = BCl 3 /SiCl 4 /Ar chemistry • Digital Etch (DE) = self-limiting O 2 plasma oxidation + H 2 SO 4 or HCl oxide removal RIE + 5 cycles DE • Radial etch rate=1 nm/cycle • Sub-20 nm NW diameter • Aspect ratio > 10 • Smooth sidewalls Zhao, IEDM 2013 Zhao, EDL 2014 Zhao, IEDM 2014 6
I I I -V VNW MOSFET/ TFET process flow 7
NW-MOSFET I -V characteristics: D= 40 nm V gs =-0.2 V to 0.7 V in 0.1 V step 300 g m,pk =720 μ S/ μ m 800 250 700 V d = 0.5 V 200 600 I s (µ A/ µ m) g m ( µ S/ µ m ) 500 150 400 100 300 200 50 100 0 0 0.0 0.1 0.2 0.3 0.4 0.5 -0.2 0.0 0.2 0.4 0.6 V ds (V) V gs (V) -3 10 V ds =0.5 V -4 10 -5 10 Single nanowire MOSFET: V ds =0.05 V I s ( A/ µ m ) -6 10 • L ch = 80 nm -7 10 S lin = 70 mV/dec • 3 nm Al 2 O 3 (EOT = 1.5 nm) -8 10 S sat = 80 mV/dec -9 DIBL = 88 mV/V 10 Zhao, CSW 2017 -10 10 -0.2 0.0 0.2 0.4 0.6 V gs (V) 8
Benchmark with Si/ Ge VNW MOSFETs Peak g m of InGaAs (V DS =0.5 V), Si and Ge VNW MOSFETs 1400 Si/Ge 1200 InGaAs g m,pk ( µ S/ µ m) 1000 800 1.2 V 600 Our work (V DS =0.5 V) 400 1.2 V 1 200 1 V 1 V 1V 0 0 20 40 60 80 100 Target Diameter (nm) • InGaAs competitive with Si • Need to demonstrate VNW MOSFETs with D<10 nm 9
I nGaAs VNW Mechanical Stability for D< 10 nm 8 nm InGaAs VNWs after 7 DE cycles: 8 nm InGaAs VNWs: Yield = 0% Broken NW Difficult to reach 10 nm VNW diameter due to breakage 10
I nGaAs VNW Mechanical Stability for D< 10 nm Difficult to reach 10 nm VNW diameter due to breakage 8 nm InGaAs VNWs: Yield = 0% Water-based acid is problem: Broken NW Surface tension (mN/m): • Water: 72 • Methanol: 22 • IPA: 23 Solution: alcohol-based digital etch 11
Alcohol-Based Digital Etch Lu, EDL 2017 8 nm InGaAs VNWs after 7 DE cycles: 10% HCl in IPA 10% HCl in DI water Yield = 97% Yield = 0% Broken NW Radial etch rate: 1.0 nm/cycle Radial etch rate: 1.0 nm/cycle Alcohol-based DE enables D < 10 nm 12
D= 5.5 nm VNW arrays 10% H 2 SO 4 in methanol 90% yield • H 2 SO 4 :methanol yields 90% at D=6 nm! • Viscosity matters: methanol (0.54 cP) vs. IPA (2.0 cP) 13
I nGaAs Digital Etch First demonstration of D=5 nm diameter InGaAs VNW (Aspect Ratio > 40) 14
Latest! D= 15 nm I nGaAs VNW MOSFET 200 V gs = 0 V to 0.6 V in 0.1 V step R on = 5500 Ω ⋅ µ m Mo contact 150 D = 15 nm I d (µ A/ µ m) o C N 2 RTA 300 100 50 0 0.0 0.1 0.2 0.3 0.4 0.5 V ds (V) Single nanowire MOSFET: • L ch = 80 nm • 2.5 nm Al 2 O 3 (EOT = 1.3 nm) Zhao, IEDM 2017 15
Benchmark with Si/ Ge VNW MOSFETs Peak g m of InGaAs (V DS =0.5 V), Si and Ge VNW MOSFETs Our latest work (V DS =0.5 V) Even better results at IEDM 2017! Target Most aggressively scaled VNW MOSFET ever 16
I nGaAs/ I nAs heterojunction VNW TFETs @ MI T Top-down approach: flexible and manufacturable 17
Gen-2 I nGaAs VNW-TFET Single NW: D= 40 nm, L ch = 60 nm, 3 nm Al 2 O 3 (EOT = 1.5 nm) New step: final RTA → 10 fold reduction in D it V gs = 0 V to 0.6 V in 0.1 V step 2.0 0 10 V gs =0 V to 0.6 V in 0.1 V step -1 10 1.5 -2 10 I d (µ A/ µ m) I d (µ A/ µ m) 1.0 -3 10 -4 10 0.5 -5 10 -6 0.0 10 -0.4 -0.2 0.0 0.2 0.4 0.0 0.1 0.2 0.3 0.4 0.5 V ds (V) V ds (V) • Saturated output characteristics • Clear negative differential resistance • Peak to valley ratio of 3.4 @ V gs = 0.6 V Zhao, EDL 2017 18
NW-TFET subthreshold characteristics -5 150 10 V d =0.3 V T=300 K 140 -6 10 130 120 -7 10 S (mV/dec) I d ( A/ µ m ) V d =0.05 V 110 -8 10 100 90 -9 10 80 V d = 0.05 V -10 10 70 V d = 0.3 V 60 -11 10 50 -11 -10 -9 -8 -7 -6 0.0 0.1 0.2 0.3 0.4 0.5 10 10 10 10 10 10 I d (A/ µ m) V gs (V) • Sub-thermal for 2 orders of magnitude of current • S lin = 55 mV/dec • S sat = 53 mV/dec Zhao, EDL 2017 19
Random Telegraph noise (RTN) in TFETs V ds = 50 mV -2 10 3n Welch V gs = 0.24 V 1/f2 2n 1/f 2n -1 ) I d ( A ) d ( Hz 2n -3 V ds =0.3 V 10 -5 10 2 2n SI d /I Jump -6 10 2n -7 1n 10 I d ( A/ µ m ) V ds =0.05 V -4 10 1n -8 10 S lin = 61 mV/dec 1n -9 0 1 10 0 10 20 30 40 10 10 S sat = 66 mV/dec f [Hz] Time [S] -10 10 V ds = 50 mV -11 -2 10 900p 10 Welch V gs = 0.18 V 0.0 0.1 0.2 0.3 0.4 0.5 0.6 1/f2 V gs (V) 800p 1/f 700p -1 ) I d ( A ) d ( Hz -3 10 600p 2 SI d /I 500p 400p -4 10 300p 0 10 20 30 40 0 1 10 10 Time [S] f [Hz] • RTN consistent with jump in subthreshold current • Single-trap behavior visible 20
Conclusions • Improved InGaAs etching technology: sub-10 nm nanowires with very high aspect ratio and high yield • InGaAs VNW MOSFETs with record characteristics • InGaAs VNW TFETs with subthermal behavior over 2 orders of magnitude of I D • Exciting new results to be presented at IEDM 2017 21
Recommend
More recommend
