Performance and Design Considerations for Gate-All-around - - PowerPoint PPT Presentation
Performance and Design Considerations for Gate-All-around Stacked-NanoWires FETs S. Barraud, V. Lapras, B. Previtali, M.P. Samson, J. Lacord, S. Martinie, M.-A. Jaud, S. Athanasiou, F. Triozon, O. Rozeau, J.M. Hartmann, C. Vizioz, C.
M.-A. Jaud, S. Athanasiou, F. Triozon, O. Rozeau, J.M. Hartmann, C. Vizioz, C. Comboroure, F. Andrieu, J.C. Barbé, M. Vinet, and T. Ernst CEA-LETI, Minatec Campus, Grenoble, France STMicroelectronics, Crolles, France
22nm INTEL 14nm INTEL 16nm TSMC 14nm SAMSUNG
3D FinFET 2D FDSOI
28nm ST 22nm GF
Back-gate control using thin BOX capacitive Single-gate reduction
thinner TSi or TBOX
New MOSFET architectures need to be proposed
Two main MOSFET architectures for advanced CMOS
2.
Max M. Shulaker et al., Nature 2017, Stanford
Plenty of space … at the top !
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May │ 2017 Samsung set to lead the future of foundry with comprehensive process roadmap down to 4nm 4LPP (4nm Low Power Plus): 4LPP will be the first implementation of next generation device architecture – MBCFETTM structure (Multi Bridge Channel FET). MBCFETTM is Samsung’s unique GAAFET (Gate All Around FET) technology that uses a Nanosheet device to overcome the physical scaling and performance limitations of the FinFET architecture. https://news.samsung.com/global/samsung-set-to-lead-the-future-of-foundry-with- comprehensive-process-roadmap-down-to-4nm June │ 2017 IBM claims 5nm Nanosheet breakthough IBM researchers and their partners have developed a new transistor architecture based on Stacked
Silicon Nanosheets that they believe will make FinFETs obsolete at the 5nm node
http://www.eetimes.com/document.asp?doc_id=1331850&
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15 years of innovation
IEDM06
First Stacked NW CMOS
10-14 10-12 10-10 10-8 10-6 10-4
0.5 1 1.5 2 Drain Current ID (A) Gate 1 voltage VG1 (V)
VD=50mV L=550nm
VG2=0.8 to -1.4V step = -0.2V
3T-FET 4T-FET
SS=62mV/dec. SS=82mV/dec.
VG2 VG1 VS VD 4T-FET
VG VD 3T-FET
exx eyy
Si0.7Ge0.3 Si0.7Ge0.3 Si0.7Ge0.3 Si0.7Ge0.3e e
Si0.7Ge0.3
Si channel Si channelInner spacer Si0.7Ge0.3
In-plane deformation Out-of-plane deformation
b
Nanowires with independent gates Internal spacers introduction ONO crystalline 3D Flash Strain booster High density 13 crystalline levels !
VLSI 08 LETI - STM
IEDM 2008 -LETI
IEDM 2016
IEDM 2008
IBM
MultiBridge Channel MOSFET
S.Y. Lee et al SAMSUNG IEEE Trans Nano 2003
10 15 20 25 30 35 40 20 40 60
DIBL (mV/V) Gate length (nm)
14nm INTEL [1]
Fin FETs GAA Wire FETs
[2] H. Mertens et al., VLSI Technology, 2016. [1] S. Natarajan et al., IEDM, 2014.
IMEC [2]
GAA 7nm
LG=10nm
W=7nm, HFin=45nm
FinFET
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TCAD
Same process (LETI 2008 – IEDM)
Switching delay, ps
Energy per switch, fJ
Alternative
structures
ELECTROSTATICS FF/NW/NS MOBILITY FF/NW/NS
CPARASITICS
FF/NW/NS
3 Fins
Layout Footprint (LF) Metal Gate Fins Contact FP CPP
Device architecture scaling
CPP scaling LG reduction Electrostatic booster to keep low leakage current
Device Fabrication
FF/NW/NS
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8.
0,2 0,4 0,6 0,8 40 80 120
NW FF
Weff=circonference of Fin (2HFin+W)
TCAD
9.
Layout footprint (nm) Layout footprint (nm)
FF W=7nm
HFin=43nm
0,2 0,4 0,6 0,8 40 80 120
NW FF Layout footprint (nm)
Layout footprint (nm)
Weff=circonference of Fin (2HFin+W)
FF NW
W=7nm HFin=43nm
10.
?
TCAD
0,2 0,4 0,6 0,8 40 80 120
NW NS FF
Weff=circonference of Fin (2HFin+W) 11.
82nm 57nm 32nm 107nm 132nm W=82nm W=32nm W=15nm
+5% weff +24% weff +42% weff x3GAA
WNS
20 40 60 80 100 120 140 30 40 50 60
DIBL (mV/V) WNS (nm)
12.
FinFET (HFin=43nm, W=7nm)
TCAD (LG=16nm)
Electrostatics of multi-gates MOSFET transistors
1st boundary condition
20 40 60 80 100 120 140 30 40 50 60
DIBL (mV/V) WNS (nm)
13.
FinFET (HFin=43nm, W=7nm)
Electrostatics of multi-gates MOSFET transistors
1st boundary condition 2nd boundary condition
→ Optimal electrostatics control!
NW
TCAD (LG=16nm)
20 40 60 80 100 120 140 30 40 50 60
DIBL (mV/V) WNS (nm)
14.
FinFET (HFin=43nm, W=7nm)
Electrostatics of multi-gates MOSFET transistors
1st boundary condition NW 2nd boundary condition
between NW and FinFET. DIBL depends on wire width (W).
TCAD (LG=16nm)
LG=13nm LF=57nm
FF
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FF NW NS
0,2 0,4 20 30 40 50 60
DIBL (mV/V) Weff (µm)
0,4 0,6 20 30 40 50 60
DIBL (mV/V) Weff (µm)
0,4 0,6 20 30 40 50 60
DIBL (mV/V) Weff (µm)
LG=13nm LF=82nm LG=13nm LF=107nm
FF FF
NW NW NW
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0,5 1,0 1,5 10
10
10
LF=57nm LF=82nm LF=107nm
FP=25nm 3 stacked GAA LG=16nm HNW=6.5nm
FF LP HP
W=7nm 13nm 15nm 19.5nm 24nm 32nm 57nm
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t: Delay Ieff: Effective drive current Ieff=(IH+IL)/2 IH=IDS(VGS=VDD, VDS=VDD/2) IL=IDS(VGS=VDD/2, VDS=VDD) Supply voltage VDD=0.7V FO=3 LG=16nm Spacer size: 4.2nm EOT=0.67nm Cback-end=2fF M=2: Miller effect in inverter
FF NW
20 40
10 20
Ceq (%) Ceq (%) tp (%) tp (%)
LF=82nm (4 Fins with FP=25nm) LF=57nm (3 Fins with FP=25nm) 57nm 19.5nm 82nm 32nm 15.3nm NW (W=7nm)
Ceq is reduced for NWs (W=7nm) but no delay reduction is achieved, while performance can be significantly improved for nanosheet design having wider
20% is expected for WNS~30nm
2 3 4 5 6 7 8 9 10 11 10 20 30 40 50 60 70 80
tp reduction (%)
Number of stacked GAA
0.5fF 1fF 2fF 4fF 6fF
HFin=29nm HFin=72nm HFin=115nm
High Ieff Increase vs Ceq increase
LF=57nm W=19.5nm VDD=0.7V
Saturation of tp reduction when the number of stacked nanowires increase (Ieff increase from N to N+1 is close to Ceq increase).
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In GAA NanoSheet, µelectron is increased due to high mobility in the (100) plan.
FF mobility
19.
FF mobility
Horizontal GAA NS for n-FETs and vertical GAA NS for p-FETs turn out to be the most effective solutions to promote electron and hole transport, respectively. [110] FinFET
20.
– Precession Electron Diffraction
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xN-(SiGe/Si) EPI Growth (Si0.7Ge0.3/Si) Fin Patterning TEOS/Poly-Si Dummy Gate CMP Poly-Si Dummy Gate Patterning
RMG Process 300mm (100) SOI substrates
(Si/SiGe) multilayer: Option1:
(Si/SiGe/Si) ≡ (12nm/12nm/12nm)
Option2:
(Si/SiGe/Si/SiGe/Si) ≡ (7nm/8nm/7nm/8m/7nm)
Spacer 0 Deposition/Etch Inner Spacer Deposition/Etch S/D EPI Growth Spacer 1 Deposition/Etch ILD and CMP Dummy Gate removal Release of stacked-NW RMG module HfO2/TiN/W Contact BEOL modules
Horizontal Wires
1. 2. 3. 4. 5.
Grey steps are not different that FinFET process-Flow
22.
Superlattice (SiGe/Si) Fin Patterning Dummy Gate Deposition & RIE Spacer Deposition and RIE Source/Drain Epitaxy ILD & CMP Dummy Gate Removal Formation of Suspended NW (release of NW) Gate Stack Formation Contact/BEOL Inner spacer formation Vertically stacked wires FETs Process-Flow
23.
Superlattice (SiGe/Si) Fin Patterning Dummy Gate Deposition & RIE Spacer Deposition and RIE Source/Drain Epitaxy ILD & CMP Dummy Gate Removal Formation of Suspended NW (release of NW) Gate Stack Formation Contac/BEOL Inner spacer formation Vertically stacked wires FETs Process-Flow Individual and dense arrays of fins were patterned to fabricate stacked wires FETs. 40 nm Fin pitch / 60 nm height / 20 nm width
24.
Superlattice (SiGe/Si) Fin Patterning Dummy Gate Deposition & RIE Spacer Deposition and RIE Source/Drain Epitaxy ILD & CMP Dummy Gate Removal Formation of Suspended NW (release of NW) Gate Stack Formation Contac/BEOL Inner spacer formation Vertically stacked wires FETs Process-Flow
Not different that FinFET
SiO2/Poly-Si Dummy Gate spacer
25.
Superlattice (SiGe/Si) Fin Patterning Dummy Gate Deposition & RIE Spacer Deposition and RIE Source/Drain Epitaxy ILD & CMP Dummy Gate Removal Formation of Suspended NW (release of NW) Gate Stack Formation Contac/BEOL Inner spacer formation Vertically stacked wires FETs Process-Flow
1. 2. 3. 4. 5.
Definition and benefit of inner spacer ?
13.
5.
Si Si SiGe
Fin recess SiGe etching Inner spacer Raised- S/D
Superlattice (SiGe/Si) Fin Patterning Dummy Gate Deposition & RIE Spacer Deposition and RIE Source/Drain Epitaxy ILD & CMP Dummy Gate Removal Formation of Suspended NW (release of NW) Gate Stack Formation Contac/BEOL Inner spacer formation Vertically stacked wires FETs Process-Flow After the Fin recess Fin recess SiGe etching
27.
Superlattice (SiGe/Si) Fin Patterning Dummy Gate Deposition & RIE Spacer Deposition and RIE Source/Drain Epitaxy ILD & CMP Dummy Gate Removal Formation of Suspended NW (release of NW) Gate Stack Formation Contac/BEOL Inner spacer formation Vertically stacked wires FETs Process-Flow
10 20 30 40 50 60 20 40 60 80 100 120 140
SiGe Etching (nm) Time (sec)
Etch rate Ge 45% Ge 30%
Second step
Etch depth profile with Si 7nm and SiGe 8nm 28.
Superlattice (SiGe/Si) Fin Patterning Dummy Gate Deposition & RIE Spacer Deposition and RIE Source/Drain Epitaxy ILD & CMP Dummy Gate Removal Formation of Suspended NW (release of NW) Gate Stack Formation Contac/BEOL Inner spacer formation Vertically stacked wires FETs Process-Flow The depth of the SiGe recess was adjusted to match the thickness of future inner spacers 50nm
29.
Superlattice (SiGe/Si) Fin Patterning Dummy Gate Deposition & RIE Spacer Deposition and RIE Source/Drain Epitaxy ILD & CMP Dummy Gate Removal Formation of Suspended NW (release of NW) Gate Stack Formation Contac/BEOL Inner spacer formation Vertically stacked wires FETs Process-Flow
LG=20nm Spacer=9nm TSi=12nm TSiGe=12nm
30.
Which benefits for parasitic capacitances?
IBM
GAA nanosheet (x3) TSi=5nm TSiGe=10nm 44/48 CPP ground rules
CEA-LETI
10 15 20 25 30 35
CGD reduction (%) NW width (nm)
31.
ing
NW NS
TCAD
Superlattice (SiGe/Si) Fin Patterning Dummy Gate Deposition & RIE Spacer Deposition and RIE Source/Drain Epitaxy ILD & CMP Dummy Gate Removal Formation of Suspended NW (release of NW) Gate Stack Formation Contac/BEOL Inner spacer formation Vertically stacked wires FETs Process-Flow
In-situ Boron doped SiGe(:B) Source/Drain In-situ Phosphorus doped Si(:P) Source/Drain
32.
33.
NW/NS Cross-section Along source-drain direction
Si channel Si channel
Inner spacer
SiGe SiGe Short-LG (20nm) Long-LG (>300nm)
After HfO2/TiN/W deposition (LG=200nm)
LETI
Superlattice (SiGe/Si) Fin Patterning Dummy Gate Deposition & RIE Spacer Deposition and RIE Source/Drain Epitaxy ILD & CMP Dummy Gate Removal Formation of Suspended NW (release of NW) Gate Stack Formation Contac/BEOL Inner spacer formation
1. 2. 3. 4.
* M.P . Vigouroux et al., APL 105, 191906 (2014)
Strain maps were obtained by TEM using Precession Electron Diffraction technique*
* D. Cooper et al., Nano Lett. 15, 5289 (2015)
Strain engineering is another key factor for stacked-wires FETs.
34.
35.
36.
The substrate induced-strain (~1.4-GPa biaxial stress: exx=0.77%) is well transferred in the stack.
37.
EDX - Si EDX - Ge
100 200 300 400 500 0,0 0,4 0,8 1,2
Distance (nm)
Measurement in sSi channels Relaxation of sSi (free edges)
C1 C2 C3
100 200 300 400 500 0,0 0,4 0,8 1,2
Distance (nm)
Relaxation of SiGe (free edges) Measurement in SiGe channels
S1 S2
+0.4 0.0
(s)Si
Fin width Along the source-drain direction
38.
e e
Si Si
exx
Si Si
eyy
Si channel Si channel
Si Si
Inner spacer
In-plane deformation Out-of-plane deformation
a
Dummy gate
The silicon channels as well as the source and drain are unstrained A deformation close to 0% is observed
0 10 20 30 40 50 60 70 80
0,0 0,5 1,0 1,5 Deformation (%) Channel
Top channel Bottom channel
Source Drain Channel
In-plane (exx) PED deformation maps of stacked-wire transistor. Here, inner spacer and Si source/drain are considered.
39.
e e
Si Si
exx
Si Si
eyy
Si channel Si channel
Si Si
Inner spacer
In-plane deformation Out-of-plane deformation
a
Dummy gate
0 10 20 30 40 50 60 70 80
0,0 0,5 1,0 1,5 Deformation (%) Channel
Top channel Bottom channel
Source Drain Channel
Full strain relaxation of sacrificial Si0.7Ge0.3 layer after the Fin recess In-plane (exx) PED deformation maps of stacked-wire transistor. Here, inner spacer and Si source/drain are considered.
40.
An initial strain (substrate-induced strain) is useless
exx eyy
Si0.7Ge0.3 Si0.7Ge0.3 Si0.7Ge0.3 Si0.7Ge0.3
e e
Si0.7Ge0.3
Si channel Si channel
Inner spacer Si0.7Ge0.3
In-plane deformation Out-of-plane deformation
b
In-plane (exx) PED deformation maps of stacked-wire transistor. Here, inner spacer and SiGe source/drain are considered.
Optimized engineering of process-induced stress techniques such as SiGe S/Ds (for p-FET) can be efficient in 3D stacked-NWs devices
0 10 20 30 40 50 60 70 80 90
0,0 0,5 1,0 Deformation (%) Channel
channel source drain Si SiGe SiGe
top bottom
41.
– Precession Electron Diffraction
42.
43.
44.
Feasibility of Mo(W)S2 synthesis ALD demonstrated
Screening of dedicated precursors, H2S free
450°C 800°C
MoS3,3C4,7H12N
S.Cadot et al J. Vac. Sci. Technol. A, Nov/Dec 2017, 061502
45.
are now demonstrated (inner spacers, SiGe:B S/D, 44/48 CPP)
fabricated with minimal deviation from FinFET (FF) devices in contrast to vertical NWs which require more disruptive technological changes
Efficiency of process-induced strain (SiGe S/D) significant compressive strain (~0.5 to 1%) in top and bottom Si p-channels
designers for the power-performance optimization thanks to a fine tuning of the device width.
46.
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