Vertical Nanowire I nGaAs MOSFETs Fabricated by a Top-down Approach - - PowerPoint PPT Presentation

Vertical Nanowire I nGaAs MOSFETs Fabricated by a Top-down Approach

Xin Zhao, Jianqiang Lin, Christopher Heidelberger, Eugene A. Fitzgerald and Jesús A. del Alamo

Microsystems Technology Laboratories, MIT

December 11, 2013 Sponsors: NSF Award #0939514 (E3S STC) Fabrication: MTL, SEBL at MIT

Outline

• Motivation
• Device technology
• Device electrical characteristics
• Conclusions

2

Motivation

Superior electron transport properties of InGaAs material system – high mobility and electron velocity

del Alamo, Nature 2011

3

Gate-all-around (GAA) nanowire MOSFETs

• Nanowire MOSFET provides ultimate scalability

Kuhn, TED 2012

4

Vertical channel MOSFETs

Vertical nanowire decouples footprint scaling and gate length scaling  high density

Liu, DRC 2012

• Use of vertical FETs saves 40% of total chip area

5

Persson, DRC 2012 Tomioka, Nature 2012 Tanaka, APEX 2010

Bottom-up approach

Impressive devices via bottom-up techniques demonstrated

• Complicated epitaxial growth or Au seed particles

required

• Top-down approach worth investigating!

6

Goal: vertical nanowire I nGaAs MOSFETs fabricated via top-down approach

Key elements:

• Top-down approach based on RIE
• Single nanowire MOSFETs

Mo/Ti/Au SOG W i n+ n+ InGaAs Al2O3

n+ InGaAs, 70 nm i InGaAs, 80 nm n+ InGaAs, 300 nm

Starting heterostructure: n+: 6×1019 Si doping

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Adhesion layer HSQ n+ Starting substrate InGaAs i

Process flow

n+ n+ i n+ Sputtered W ALD-Al2O3 1st SOG 2nd SOG

Mo/Ti/Au

Tomioka, Nature 2012 Persson, DRC 2012

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Key enabling technology: RI E by BCl3/ SiCl4/ Ar Chemistry

• Sub-20 nm resolution
• Aspect ratio > 10
• Smooth sidewall and surface
• BCl3/SiCl4/Ar RIE chemistry used for III-V optical

devices, never used for nm-scale features

20 nm

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Critical parameter: Substrate temperature during RI E

T↑  etch rate↑, surface roughness↓, sidewall verticality ↑

10

Nanowire RI E followed by digit al e

et ch

• Shrinks NW diameter by 2 nm per cycle
• Unchanged shape
• Reduced roughness

Digital etch:

• self-limiting O2 plasma oxidation + H2SO4 oxide removal

before after 10 cycles

Lin, IEDM 2012

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After 1st planarization After 2nd planarization

Planarization and etch back

50 nm 30 nm 50 nm 40 nm W gate metal SOG

1st SOG 2nd SOG W ALD-Al2O3

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NW-MOSFET I -V characteristics D= 30 nm

Single nanowire MOSFET:

• D= 30 nm
• Lch= 80 nm
• 4.5 nm Al2O3 (EOT = 2.2 nm)

At VDS=0.5 V (normalized by periphery):

• gm,pk=280 μS/μm
• Ron=759 Ω.μm

0.0 0.1 0.2 0.3 0.4 0.5 Vds (V)

Vgs=-0.6 V to 0.8 V in 0.1 V step Ron=759 Ω.µm (at Vgs=1 V)

50 100 150 200

Id (µA/µm

)

• 0.6 -0.4 -0.2 0.0

0.2 0.4 0.6 50 100 150 200

Vgs (V)

50 100 150 200 250 300

gm, pk(Vds=0.5 V) =280 µS/µm

Vds=0.5 V Id (µA/µm) gm (µS/µm)

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D= 30 nm I nGaAs NW-MOSFETs

• 0.6 -0.4 -0.2 0.0

0.2 0.4 0.6

Vds=0.05 V

Vgs (V)

Vds=0.5 V Ig< 10-9 A/µm DIBL=195 mV/V S=145 mV/dec, Vds=0.05 V S=200 mV/dec, Vds=0.5 V

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• 8

10

• 7

10

• 6

10

• 5

10

• 4

Id (A/µm)

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D= 50 nm I nGaAs NW-MOSFET

At Vds=0.5 V:

• gm,pk=730 μS/μm
• Ron=310 Ω.μm
• 1.0-0.8-0.6-0.4-0.2 0.0 0.2 0.4

100 200 300 400 500 600

Id (µA/µm)

gm, pk(Vds=0.5 V) =730 µS/µm Vds=0.5 V

Vgs(V)

100 200 300 400 500 600 700

gm (µS/µm)

0.0 0.1 0.2 0.3 0.4 0.5

Vds (V)

Vgs=-0.6 V to 0.8 V in 0.1 V step Ron=310 Ω.µm (at Vgs=1 V)

100 200 300 400 500 600 700

Id (µA/µm

)

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D= 50 nm I nGaAs NW-MOSFETs

• 0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8

Vgs(V)

DIBL=360 mV/V S=210 mV/dec, Vds=0.05 V S=305 mV/dec, Vds=0.5 V Ig< 10-10 A/µm Vds=0.5 V Vds=0.05 V

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• 6

10

• 5

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• 4

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• 3

Id (A/µm)

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I mpact of nanowire diameter

D↓  S↓, DIBL↓, gm↓, Ron↑

Error bars indicate distribution of ~10 devices

30 35 40 45 50 150 200 250 300 350

S (mV/dec) Diameter (nm)

Vds=0.5 V Vds=0.05 V

30 35 40 45 50 150 200 250 300 350 400 450

Diameter (nm) DIBL (mV/V)

30 35 40 45 50 200 400 600 800

gm (µS/µm)

Diameter (nm) Vds=0.5 V

30 35 40 45 50 200 400 600 800 1000 1200

Vgs=1 V

Ron (Ω.µm)

Diameter (nm)

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I mpact of digital etch

• 0.5 -0.4 -0.3 -0.2 -0.1 0.0

0.1 0.2 100 200 300 400 500

no digital etch

Vds=0.5 V digital etch Vgs(V) gm (µS/µm)

Digital etch  S↓, gm↑, Ig↓

• Better sidewall interface
• Ron and DIBL unchanged
• 0.6
• 0.4
• 0.2

0.0 0.2 0.4

digital etch no digital etch Vgs(V)

Vds=0.5 V Vds=0.05 V

10

• 7

10

• 6

10

• 5

10

• 4

Id (A/µm)

• 1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4

10

• 6

10

• 5

10

• 4

10

• 3

Vds=1 V

Ig (A/cm2) Vgs(V)

digital etch

no digital etch

Single nanowire MOSFET:

• D= 40 nm (final diameter)

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Benchmarking against bottom-up vertical I nGaAs NW-MOSFETs

• Fundamental trade-off between transport and short-channel effects
• Top-down NW-MOSFETs as good as bottom up devices

Persson, DRC 2012 Tomioka, Nature 2012

200 400 600 200 400 600 800 1000 1200

Vds=0.5 V

S(mV/dec)

gm,pk(µS/µm)

Tanaka, APEX 10

Tomioka, IEDM 11 Tomioka, Nature 12 Persson, DRC 12 Persson, EDL 10

This work (Top down)

Bottom up This work Tanaka, APEX 2010 Persson, EDL 2012

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Conclusions

• First demonstration of top-down III-V GAA NW-

MOSFET with vertical channel

• Novel III-V RIE process with sub-20 nm resolution
• 30 nm diameter NW MOSFET achieved
• Digital etch improves subthreshold and transport

characteristics

• Device performance matches that of best bottom-up

vertical NW III-V MOSFETs

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Acknowledgement

• NSF E3S
• Fabrication facility at MIT labs: MTL, SEBL
• MIT colleagues: T. Yu, L. Guo, W. Chern, A. Vardi, L. Xia, D.

Antoniadis, J. Hoyt, D. Jin, A. Guo, S. Warnock, W. Lu, Y. Wu, J. Teherani

• E3S colleagues: A. Lakhani, S. Agarwal, M. Eggleston, E.

Yablonovitch, M. Wu

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