Vertical Nanowire I nGaAs MOSFETs Fabricated by a Top-down Approach Xin Zhao, Jianqiang Lin, Christopher Heidelberger, Eugene A. Fitzgerald and Jesús A. del Alamo Microsystems Technology Laboratories, MIT December 11, 2013 Sponsors: NSF Award #0939514 (E3S STC) Fabrication: MTL, SEBL at MIT
Outline • Motivation • Device technology • Device electrical characteristics • Conclusions 2
Motivation Superior electron transport properties of InGaAs material system – high mobility and electron velocity del Alamo, Nature 2011 3
Gate-all-around (GAA) nanowire MOSFETs Kuhn, TED 2012 • Nanowire MOSFET provides ultimate scalability 4
Vertical channel MOSFETs Vertical nanowire decouples footprint scaling and gate length scaling high density Liu, DRC 2012 • Use of vertical FETs saves 40% of total chip area 5
Bottom-up approach Impressive devices via bottom-up techniques demonstrated Complicated epitaxial growth or Au seed particles • required Tanaka, APEX 2010 Tomioka, Nature 2012 Persson, DRC 2012 • Top-down approach worth investigating! 6
Goal: vertical nanowire I nGaAs MOSFETs fabricated via top-down approach Mo/Ti/Au n+ Starting heterostructure: SOG Al 2 O 3 n+ InGaAs, 70 nm W i i InGaAs, 80 nm n+ InGaAs, 300 nm n+: 6 × 10 19 Si doping n+ InGaAs Key elements: • Top-down approach based on RIE • Single nanowire MOSFETs 7
Tomioka, Nature 2012 Process flow Persson, DRC 2012 Sputtered W Starting substrate ALD-Al 2 O 3 n+ InGaAs i n+ Adhesion 1 st SOG HSQ layer n+ i n+ 2 nd SOG Mo/Ti/Au 8
Key enabling technology: RI E by BCl 3 / SiCl 4 / Ar Chemistry 20 nm • Sub-20 nm resolution • Aspect ratio > 10 • Smooth sidewall and surface • BCl 3 /SiCl 4 /Ar RIE chemistry used for III-V optical devices, never used for nm-scale features 9
Critical parameter: Substrate temperature during RI E T ↑ etch rate ↑, surface roughness↓, sidewall verticality ↑ 10
Nanowire RI E followed by digit al e et ch Lin, IEDM 2012 Digital etch: self-limiting O 2 plasma oxidation + H 2 SO 4 oxide removal • after 10 cycles before • Shrinks NW diameter by 2 nm per cycle • Unchanged shape • Reduced roughness 11
Planarization and etch back After 1 st planarization 1 st SOG 50 nm W 40 nm W gate metal SOG ALD-Al 2 O 3 After 2 nd planarization 2 nd SOG 50 nm 30 nm 12
NW-MOSFET I -V characteristics D= 30 nm V gs =-0.6 V to 0.8 V in 0.1 V step R on =759 Ω.µ m (at V gs =1 V) 200 200 300 g m, pk (V ds =0.5 V) =280 µ S/ µ m 250 150 I d ( µ A/ µ m ) g m ( µ S/ µ m) 150 ) I d ( µ A/ µ m 200 100 150 100 100 V ds =0.5 V 50 50 50 0 0 0 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.0 0.1 0.2 0.3 0.4 0.5 V gs (V) V ds (V) At V DS =0.5 V (normalized by Single nanowire MOSFET: periphery): • D= 30 nm • g m,pk =280 μ S/ μ m • L ch = 80 nm • R on =759 Ω . μ m • 4.5 nm Al 2 O 3 (EOT = 2.2 nm) 13
D= 30 nm I nGaAs NW-MOSFETs V ds =0.5 V -4 10 I g < 10 -9 A/ µ m I d ( A/ µ m ) -5 10 V ds =0.05 V -6 10 DIBL=195 mV/V -7 S=145 mV/dec, V ds =0.05 V 10 S=200 mV/dec, V ds =0.5 V -8 10 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 V gs (V) 14
D= 50 nm I nGaAs NW-MOSFET V gs =-0.6 V to 0.8 V in 0.1 V step 700 700 R on =310 Ω.µ m (at V gs =1 V) 600 600 g m, pk (V ds =0.5 V) 600 500 =730 µ S/ µ m 500 ) g m ( µ S/ µ m) I d ( µ A/ µ m 500 I d ( µ A/ µ m ) 400 400 400 300 300 300 V ds =0.5 V 200 200 200 100 100 100 0 0 0 -1.0-0.8-0.6-0.4-0.2 0.0 0.2 0.4 0.0 0.1 0.2 0.3 0.4 0.5 V gs (V) V ds (V) At V ds =0.5 V: • g m,pk =730 μ S/ μ m • R on =310 Ω . μ m 15
D= 50 nm I nGaAs NW-MOSFETs -3 10 V ds =0.5 V I g < 10 -10 A / µ m -4 10 V ds =0.05 V I d ( A/ µ m ) -5 10 DIBL=360 mV/V S=210 mV/dec, V ds =0.05 V S=305 mV/dec, V ds =0.5 V -6 10 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 V gs (V) 16
I mpact of nanowire diameter 450 350 400 V ds =0.5 V S (mV/dec) DIBL (mV/V) 300 350 250 300 250 200 200 V ds =0.05 V 150 150 30 35 40 45 50 30 35 40 45 50 Diameter (nm) Diameter (nm) Error bars 800 1200 indicate g m ( µ S/ µ m ) R on ( Ω . µ m) 1000 distribution of 600 ~ 10 devices 800 400 600 200 V ds =0.5 V 400 V gs =1 V 200 30 35 40 45 50 30 35 40 45 50 Diameter (nm) Diameter (nm) D↓ S↓, DIBL↓, g m ↓, R on ↑ 17
I mpact of digital etch Single nanowire MOSFET: 500 digital etch • D= 40 nm (final diameter) 400 g m ( µ S/ µ m) 300 V ds =0.5 V no digital etch -4 200 10 100 V ds =0.05 V I d (A/ µ m) V ds =0.5 V -5 10 0 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1 0.2 V gs (V) -6 10 digital etch V ds =1 V -3 10 no digital etch -7 10 I g (A/cm 2 ) no digital etch -4 -0.6 -0.4 -0.2 0.0 0.2 0.4 10 V gs (V) digital etch -5 10 Digital etch S↓, g m ↑ , I g ↓ • Better sidewall interface -6 10 -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 • R on and DIBL unchanged V gs (V) 18
Benchmarking against bottom-up vertical I nGaAs NW-MOSFETs Tanaka, APEX 10 Tomioka, IEDM 11 Bottom up Tomioka, Nature 12 1200 Persson, DRC 12 Persson, EDL 10 1000 g m,pk ( µ S/ µ m ) This work (Top down) 800 Persson, EDL 2012 Persson, DRC 2012 600 This work 400 200 V ds =0.5 V 0 200 400 600 S(mV/dec) Tanaka, APEX 2010 Tomioka, Nature 2012 • Fundamental trade-off between transport and short-channel effects • Top-down NW-MOSFETs as good as bottom up devices 19
Conclusions • First demonstration of top-down III-V GAA NW- MOSFET with vertical channel • Novel III-V RIE process with sub-20 nm resolution • 30 nm diameter NW MOSFET achieved • Digital etch improves subthreshold and transport characteristics • Device performance matches that of best bottom-up vertical NW III-V MOSFETs 20
Acknowledgement • NSF E3S • Fabrication facility at MIT labs: MTL, SEBL • MIT colleagues: T. Yu, L. Guo, W. Chern, A. Vardi, L. Xia, D. Antoniadis, J. Hoyt, D. Jin, A. Guo, S. Warnock, W. Lu, Y. Wu, J. Teherani • E3S colleagues: A. Lakhani, S. Agarwal, M. Eggleston, E. Yablonovitch, M. Wu 21
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