A CMOS-Compatible Fabrication Process for Scaled Self-Aligned I - - PowerPoint PPT Presentation

A CMOS-Compatible Fabrication Process for Scaled Self-Aligned I nGaAs MOSFETs

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Jianqiang Lin Dimitri Antoniadis and Jesús del Alamo

Microsystems Technology Laboratories, MIT CS MANTECH, May 18-21, 2015

Acknowledgements: DTRA NSF E3S STC MIT SMART program

Motivation for III-V CMOS

• Superior electron transport properties for III-Vs

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• III-V’s: promising to extend Moore’s Law
• Focus of this talk: InGaAs MOSFET fabrication technology

Vinj: source injection velocity

Self-aligned recessed-gate QW-MOSFET

[Kim IEDM 2011]

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• Gate insulator

– thin with low leakage, low Dit

• High-level self-alignment

–

• hmic metal, access region, gate
• CMOS compatibility

– free of wet-etch, lift-off and Au

Considerations for III-V MOSFETs

2 m

HEMTs Proposed MOSFET structure:

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Process overview

W/Mo n+ cap InGaAs/InAs InAlAs SiO2 InP -Si

Mo/W ohmic contact CF4, SF6 anisotropic RIE CF4+O2 isotropic RIE [Lin, IEDM 2013] [Waldron, IEDM 2007] [Lin, APEX 2012] [Lin, IEDM 2012-2014]

Mo HfO2 Via

Gate stack Via and pad III-V recess

Resist

[Lin, IEDM 2012-2014] [Lin, IEDM 2013] [Waldron, IEDM 2007]

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Details of contact and III-V recess processes

CF4, SF6 anisotropic RIE CF4+O2 isotropic RIE [Lin, APEX 2012]

Mo HfO2 Via

Gate stack Via and pad

Resist W/Mo n+ cap InGaAs/InAs InAlAs SiO2 InP -Si

Mo/W ohmic contact III-V recess

W barrier for undercut immunity

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[Lin, IEDM 2012]

Goal: to reduce device footprint and gate pitch size

[Lin, IEDM 2012] [Lin, IEDM 2013]

(a) 20 nm Mo SiO2 Oxidized Mo

Problems with wet etch gate recess

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• Isotropic wet etch → large lateral extent

– Large footprint – Ungated and uncapped access regions → access resistance ↑

New III-V recess technology: Precise channel thickness (tc) control

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SiO2 W/Mo

n+ InGaAs/InP

InP InGaAs/InAs InAlAs Cl2 anisotropic RIE -Si

• Anisotropic

III-V dry etch: surface roughness Selected chemistry Cl2:N2

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As-grown

Key parameters:

• Bias
• Pressure
• Gas ratio (Cl2:N2)
• Gas chemistry

[Zhao EDL 2014]

Selected recipe Not selected recipes

III-V dry etch: trenching

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BCl3-chemistry

[Zhao IEDM 2014]

Low bias High bias

Cl2:N2-chemistry

New III-V recess technology: Precise channel thickness (tc) control

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SiO2 W/Mo

n+ InGaAs/InP

InP InGaAs/InAs InAlAs Cl2 anisotropic RIE Digital Etch (DE) -Si

O2 Plasma H2SO4

[Lin, EDL 2014]

• Anisotropic
• Accurate depth control

1 nm/cyc

New III-V recess technology: Precise channel thickness (tc) control

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SiO2 W/Mo

n+ InGaAs/InP

InP InGaAs/InAs InAlAs Cl2 anisotropic RIE Digital Etch (DE) -Si

O2 Plasma H2SO4

[Lin, EDL 2014]

• Anisotropic
• Accurate depth control
• Accurate and fast calibration

1 nm/cyc

Precise channel thickness (tc) control

13 0.01 0.1 1 10 200 400 600 800 DIBL (mV/V) Lg(m)

1 nm depth control Device scaling study

tc=12 nm 3 nm

tc= tc=

• ON-state: ION, gm, RSD
• OFF-state: S, DIBL, Vt roll-off

[Lin, TED submitted]

Typical long-channel characteristics

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• Steep S at low Vds → Low Dit
• Jg< 10-2 A/cm2 at EOT~0.5 nm → gate leakage suppression

(typical HEMT: Jg>100 A/cm2)

• 0.2

0.0 0.2 0.4

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• 9

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• 5

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• 4

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Id (A/m) Vgs (V)

Lg=120 nm

Vds=0.05 and 0.5 V

83 mV/dec

Scalability and performance

15 Ref: del Alamo ESSDERC 2013 (updated)

MIT MOSFETs

0.0 0.1 0.2 0.3 0.4 0.5 0.0 0.2 0.4 0.6 0.8 1.0

Lg=20 nm Ron=224 m 0.4 V

Id (mA/m) Vds (V)

Vgs-Vt= 0.5 V

Scalability Performance

[Lin, IEDM 2014]

3.1 mS/m

Conclusions

• Scalable self-aligned InGaAs MOSFETs

– CMOS manufacturability, performance, scalability

• Bilayer ohmic contact for footprint scaling
• III-V recess

– III-V dry etch: smooth surface and no trenching – Digital etch: accurate depth control

• InGaAs MOSFET performance analysis

– Steep subthreshold swing: low Dit – Gate leakage suppression – Record transconductance achieved – Working Lg=20 nm InGaAs MOSFETs

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