[PPT] - A Si-Compatible Fabrication Process for Scaled Self-Aligned InGaAs PowerPoint Presentation

SLIDE 1

A Si-Compatible Fabrication Process for Scaled Self-Aligned InGaAs FinFETs

Alon Vardi, Jianqiang Lin, Wenjie Lu, Xin Zhao and Jesús A. del Alamo

Microsystems Technology Laboratories, MIT May 23, 2017

Sponsors: DTRA (HDTRA 1‐14‐1‐0057), NSF E3S STC (grant #0939514) Lam Research

SLIDE 2

Outline

Motivation
Process technology
Electrical characteristics
Late news
Conclusions

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SLIDE 3

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Historical evolution: InGaAs High-Electron Mobility Transistor

Transconductance (gm=dID/dVGS):

Superior electron transport properties in InGaAs

High-Electron Mobility Transistor

SLIDE 4

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InGaAs MOSFETs vs. HEMTs

Transconductance (gm=dID/dVGS):

Superior electron transport properties in InGaAs

High-Electron Mobility Transistor Metal-Oxide-Semiconductor Field-Effect Transistor

SLIDE 5

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InGaAs MOSFETs vs. HEMTs

Lin, EDL 2016

gm=3.45 mS/μm Transconductance (gm=dID/dVGS):

Superior electron transport properties in InGaAs
InGaAs planar MOSFET performance exceeds that of High Electron

Mobility Transistors (HEMT)

What happened here? High-Electron Mobility Transistor Metal-Oxide-Semiconductor Field-Effect Transistor

SLIDE 6

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Huang, APL 2005

ALD eliminates residual native oxides that pin Fermi level  “Self cleaning” Clean, smooth interface without native oxides

Atomic Layer Deposition (ALD)

f gate oxide
First with Al2O3, then with other high-K dielectrics
First in GaAs, then in other III-Vs

SLIDE 7

InGaAs planar Quantum-Well MOSFETs - short-channel effects

Short‐channel effects limit scaling to Lg~40 nm
3D transistors required for further scaling

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Lin, IEDM 2014

0.01 0.1 1 10 100 150 200 250 300 Smin (mV/dec) Lg(m)

tc=12 mn VDS=0.5 V 7 mn

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Intel Si Trigate MOSFETs

FinFETs

FinFETs used in state‐of‐the‐art Si CMOS
Good balance of SCE and high ON current per footprint

SLIDE 9

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InGaAs FinFETs

Radosavljevic ,IEDM 2011 Kim, IEDM 2013

Demonstrations to date: Wf ≥ 15 nm, ARc ≤ 2

Kim, TED 2014 Thathachary, VLSI 2015 Waldron, VLSI 2014 Wf~30 nm Wf~50 nm Wf~50 nm Zota, IEDM 2016 Djara, VLSI 2015 Wf~15 nm Wf~25 nm

SLIDE 10

Goal: Sub-10 nm Wf Self-aligned III-V FinFETs

Deeply scaled Wf, Lg and EOT
High channel aspect ratio (ARc)
Self-aligned contacts
CMOS-compatible processes and materials in front-

end

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InAlAs channel cap W/Mo Lg SiO2 HSQ High ‐K

Hc Wf

ARc = Hc/Wf

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From InGaAs HEMT to finFET

100 nm del Alamo, CS MANTECH 2011 Lin, CS MANTECH 2015 Vardi, CSMANTECH 2017

Contact first
Gate recess

InGaAs HEMT InGaAs Planar MOSFET InGaAs FinFET 50nm

SLIDE 12

Fin definition: RIE + Digital etch

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30 nm 100 nm

8 nm 170 nm

BCl3/SiCl4/Ar RIE:

smooth, vertical sidewalls and high aspect ratio (>10)

Digital etch (DE):

self‐limiting O2 plasma oxidation + H2SO4 oxide removal

Zhao, EDL 2014 Vardi, VLSI 2016

SLIDE 13

Device fabrication

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30 nm In0.53Ga0.47As, Si doped 3e19 cm‐3 4 nm InP stopper 40 nm In0.53Ga0.47As, undoped

Si ‐Doping: 4e12 cm‐2

400 nm In0.52Al0.48As buffer InP semi insulating substrate

Highly doped cap
40 nm thick channel layer
Delta doping underneath

5 nm

SLIDE 14

Device fabrication

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Wf direction Lg direction InAlAs channel cap W/Mo SiO2

Sputtered W/Mo contact
CVD SiO2 hard mask

SLIDE 15

Device fabrication

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35 nm SiO2 W/Mo Wf direction Lg direction InAlAs channel cap W/Mo SiO2 Lg

Sputtered W/Mo contact
CVD SiO2 hard mask
Gate lithography
Gate recess (Dry):

SiO2/W/Mo

Active area definition

SLIDE 16

Device fabrication

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35 nm SiO2 W/Mo

InP W/Mo SiO2 20 nm InGaAs 60 nm

Wf direction Lg direction InAlAs channel cap W/Mo SiO2 Lg Lg

Sputtered W/Mo contact
CVD SiO2 hard mask
Gate lithography
Gate recess (Dry):

SiO2/W/Mo

Active area definition
Gate recess (Wet): Cap

etch

SLIDE 17

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HSQ Hc Hf 100 nm

Device fabrication

Sputtered Mo contact
CVD SiO2 hard mask
Gate lithography
Gate recess (Dry):

SiO2/W/Mo

Active area definition
Gate recess (Wet): Cap

etch

Fin Lithography
Fin etch

Buffer channel cap W/Mo SiO2

SLIDE 18

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HSQ Hc Hf High‐k/Mo 100 nm

20 nm

Device fabrication

Sputtered W/Mo contact
CVD SiO2 hard mask
Gate lithography
Gate recess (Dry):

SiO2/W/Mo

Active area definition
Gate recess (Wet): Cap

etch

Fin lithography
Fin etch
Digital etching
ALD gate dielectric

deposition

Mo gate sputtering

Mo HSQ

Double gate FinFET
HfO2 , gate oxide EOT = 0.6 nm

Buffer channel cap W/Mo SiO2

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Via SiO2

Gate hat

Device fabrication

Sputtered W/Mo contact
CVD SiO2 hard mask
Gate lithography
Gate recess (Dry):

SiO2/W/Mo

Active area definition
Gate recess (Wet): Cap

etch

Fin Lithography
Fin etch
Digital etching
ALD gate dielectric

deposition

Mo gate sputtering
Gate head photo and

pattern

ILD1 deposition
Via opening
Pad formation
Fin pitch: 200 nm
10-50 fins/device

SLIDE 20

0.1 0.2 0.3 0.4 0.5

VDS [V]

50 100 150 200 250

Id [ A/ m]

Long-channel characteristics, Wf=22 nm, Lg=0.5 μm

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Slin=68 mV/dec
Negligible DIBL
Good electrostatic control over dry etched sidewalls

HfO2, EOT = 0.6 nm

0.2
0.1

0.1 0.2 0.3 0.4 0.5 0.6

VGS [V]

10-12 10-10 10-8 10-6 10-4

Id [A/ m]

68 mV/dec VGS=0 to 0.75 V ΔVGS= 0.25 V VDS=0.5 V 0.05 V

SLIDE 21

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Most aggressively scaled FinFET

Wf=7 nm, Lg=30 nm, Hc=40 nm (AR=5.7), EOT=0.6 nm: Vardi, EDL 2016 At VDS=0.5 V:

gm=900 µS/µm
Ron=320 Ω.µm
Ssat=100 mV/dec
0.4
0.2

0.0 0.2 0.4 200 400 600 800 1000 VDS=0.5 V

gm max=900 S/m

gm [S/m] VGS [V]

0.5 -0.4 -0.3 -0.2 -0.1 0.0

0.1 0.2 0.3 0.4 1E-9 1E-8 1E-7 1E-6 1E-5 1E-4 1E-3

VDS=50 mV DIBL=90 mV/V

Id [A/m] VGS [V]

Ssat=100 mV/dev VDS=500 mV

0.0 0.1 0.2 0.3 0.4 0.5 100 200 300 400 500 Id [A/m]

VDS [V] VGS=-0.5 to 0.75 VGS=0.25 V

Current normalized by 2xHc

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100 200 300 400 500 600 700

0.6
0.4
0.2

0.0 0.2 0.4

EOT

VT [V] Lg [nm] 100 200 300 400 500 600 700 50 100 150 200 250 A: Al2O3, EOT=2.8 nm B:Al2O3/HfO2, EOT=1 nm C: HfO2, EOT=0.6 nm Ssat [mV/dec] Lg [nm]

EOT

60 mV/dec 100 200 300 400 500 600 700 200 400 600 800 1000 1200 1400 1600

EOT

VDS=0.5 V Wf20-22 nm

gm [S/m] Lg [nm]

EOT ↓  gm↑, Smin↓, VT rolloff↓ Classical scaling with Lg and EOT

Lg and EOT scaling (Wf~20 nm)

SLIDE 23

23 100 200 300 400 500 600 200 400 600 800 1000 1200 1400 1600  Wf= 5 nm gm max [S/m] Lg [nm] Wf=22nm

100 1000 50 100 150

Wf=7 nm Wf=12 nm Wf=17 nm Wf=22 nm

Ssat,min [mV/dec] Lg [nm]

Gate leakage contamination

Wf Scaling

Non-ideal Wf scaling

Wf ↓  gm ↓
Wf ↓  Constant Smin
Dit (~5x1012 cm-2.eV-1)
mobility degradation
line edge roughness?...

SLIDE 24

Benchmark

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gm normalized by gate periphery

Hc WF

ARc>1
Sub‐10 nm Wf

Zota, IEDM 2016 Best logic device both III‐V and Si

MIT FinFETs:

SLIDE 25

Benchmark

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Si > III‐V
MIT FinFETs > all other III‐V FInFETs

gm normalized by fin width

Wf

For gm/Wf:

20 40 60 5 10 15 20

0.32 1 1.8 0.57 0.8 5.7 3.3 2.3 1.8

InGaAs FinFETs

5.3 4.3

Si FinFETs (VDD=0.8 V)

gm/Wf [mS/m] Wf [nm]

0.63 0.6 0.23 0.66 1 0.18

VDD=0.5 V

SLIDE 26

0.1 0.2 0.3 0.4 0.5

VDS [V]

50 100 150

Id [ A/ m]

0.2

0.2 0.4 0.6 0.8

VGS [V]

100 200 300 400 500 600

gm [ S/ m]

0.2

0.2 0.4 0.6 0.8

VGS [V]

10-12 10-10 10-8 10-6 10-4

Id [A/ m]

65 mV/dec 50 mV VDS= 500 mV Ig 50 mV VDS= 500 mV

VGS= 0 to 0.5 V in 0.1 V steps

EOT=0.8 nm Lg=50 nm Wf=5 nm Hc=50 nm

Post deadline results

InP InGaAs 5nm

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SLIDE 27

Post deadline results - Benchmark

Record gm at Wf=5 nm
Record AR
Improved SCE

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SLIDE 28

Conclusions

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Novel self-aligned gate-last FinFET:

– Self-aligned gate to contact metals – CMOS process compatibility – Sub-10 nm fin width – ARc>1 – Double-gate FinFET

Excellent performance and short-channel effects in

devices with Lg=30 nm and Wf=22 nm

Demonstrated subthreshold swing of 65 mV/dec in

short channel devices

Still short of Si FinFETs performance

SLIDE 29

Thank you !

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