Ultimately Scaled CMOS: DG FinFETs? Jerry G. Fossum SOI Group - - PowerPoint PPT Presentation

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Ultimately Scaled CMOS: DG FinFETs?

Jerry G. Fossum

SOI Group Department of Electrical and Computer Engineering University of Florida Gainesville, FL 32611-6130

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Outline

❋ Introduction - CMOS Scaling ❋ Thin-BOX FD/SOI MOSFETs ❋ Pragmatic Nanoscale FinFETs ❋ Conclusions

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Projected HP CMOS Gate-Length Scaling* *2003 SIA ITRS

7nm [6nm in 2020!] [Intel: bulk-Si MOSFETs]

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Contemporary Bulk-Silicon MOSFET

Has been scaled a la Moore’s (and now, “More than Moore”) Law, but with increasingly complex boosters and body/channel doping density NB, which can no longer (i.e., for Lg < ~30nm) be adequately controlled.

Substrate/Well Body NB(x,y)

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Continued Scaling to Lg < 10nm: Undoped UTBs/Channels

n+ Source n+ Drain Gate n+ Source n+ Drain Gate

BOX

FD/SOI (n)MOSFET w/ thin BOX and GP? NO.

Complex processing/layout. Selective GPs, w/ biasing. Tuned dual-metal gate work functions. High inherent Vt:

.

Vt long

( )

1 r + ( )φc 0.6V ∼ =

(n)FinFET on SOI? YES.

Quasi-planar. Conventional processing, w/o NB. Two gates: good SCE control. Can be pragmatic.

n+

Gf

p-

n+

BOX

STI STI

p+ GP

Si Substrate

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2-D Numerical Simulations: Projected Scaling Limits

Pragmatic FinFET-CMOS can be scaled to the end of the SIA ITRS.

LP Thin-BOX/GP w/o VGP Thin-BOX/GP w/ VGP DG FinFET Leff (nm) 28 18 25/15 ∆ΦGf (mV) 450 0/-450 HP Thin-BOX/GP w/o VGP Thin-BOX/GP w/ VGP DG FinFET Leff (nm) 25 18? 15 ∆ΦGf (mV) 850 Taurus-predicted LP and HP scaling limits (Leff, which, with G-S/D underlap, can be 5-10nm longer than Lg), defined by tSi = 5nm, for thin-BOX/GP nMOSFETs and DG nFinFETs. The devices have been designed for Ioff ~ 10pA/µm and ~100nA/µm for LP and HP applications, respectively, with DIBL ≤ 100mV/V. The 18nm limit for the HP thin-BOX/GP device with VGP is questionable due to the very large ∆ΦGf (gate work-function tuning below midgap) needed; the scaling limit of 25nm without VGP is more realistic.

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Nanoscale Pragmatic-FinFET CMOS ❋ On SOI (no isolation, S-D leakage complexities). ❋ Undoped fin-UTB/channel (no RDF effects). ❋ DG, not TG (a top gate is virtually ineffective). ❋ One ~midgap metal gate (for nMOS and pMOS). ❋ No channel strain (mobilities are high without it). ❋ No high-k dielectric (relatively thick SiON is OK). ❋ G-S/D underlap (Leff(weak) > Lg, Leff(strong) ≅ Lg). ❋ S/D processing for Vt control (and underlap).

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The optimal number of gates is 2!

Two gates (DG) give good control of electrostatics (i.e., SCEs) with thicker UTB than that needed for one-gate (FD/SOI) device.

Davinci (3-D): Undoped Leff = 28nm TG fin size for SCE control; tox = 1.1nm

wSi(DG)/Leff ~ 1/2 1/5 ~ hSi(FD)/Leff hSi = wSi = Leff

0.0 0.5 1.0 1.5 2.0

wSi/Leff

0.0 0.5 1.0 1.5 2.0

hSi/Leff S = 80mV DIBL = 100mV/V Design Space FD/SOI DG hSi = wSi (⇒ easier fin)

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A third (top) gate is not very beneficial ...

(Note that the effective width (per fin) Weff = 2hSi + wSi is not appropriate.)

Davinci (w/o QM): Leff = 25nm, wSi = 13nm, tox = 1.2nm

0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 VGS (V) 10 20 30 40 50 60

IDS (µA)

DG FinFET TG FinFET 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Rf 20 40 60 80 100

∆Ion/Ion(DG) (%)

[wSi/(2hSi)] Rf ≡ hSi/wSi = 3 Weff-implied VDS=1.0V

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... due to strong bulk inversion in the undoped fin-UTB/channel.

The predicted electron density in the bulk of the undoped fin-UTB shows substantial (strong) inversion, irrespective of the top-surface condition. Activating the third gate is not beneficial nor practical.

5 10 15 20 25 30 35 z (nm) 1018 1019 n (cm-3)

DG FinFET DG FinFET w/o top gate stack TG FinFET

Buried SiO2 Si Substrate SiO2 Gate

z

VGS=VDS=1.0V

Rf = 39nm/13nm = 3

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The bulk inversion also underlies the use of thick SiON. * Bulk (a.k.a. volume) inversion is not good, but is unavoidable. * For strong inversion, it reduces the effective gate capacitance CG:

(via integration of Poisson’s equation) where xi is the average depth(s) of the inversion carriers, which is increased by bulk inversion. The deeper xi reflects lower inversion-layer capacitance, and yields lower CG and Qi.

* The quantization effect further increases xi and reduces CG. * Because of the deeper xi, increasing tox is not so detrimental to CG

(which is less than Cox = εox/tox), and hence to Qi and current.

* Further, the thicker SiON (tox) reduces the parasitic G-S/D (fringe)

capacitance, which improves speed performance significantly.

Q –

i

2 Cox 1 εoxxi εSitox

• +
• VGS

Vt – ( ) =

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The underlap is effected by engineering of the lateral doping-density profile in the S/D fin-extension.

NSD(y) [cm-3]

Lg Lext Lext 1010 1011 1012 1013 1014 1015 1016 1017 1018 1019 1020 1021 20 30 40 50 60 70 80 90 100 σL=5nm 10nm 15nm 1nm

y [nm] σL [nm] DIBL [mV/V] S [mV] 1 (abrupt) 180 94 5 35 62 10 46 66 15 79 71 NSD y ( ) 1020 y σL

• 

   2 – exp ∝ Medici: Straggle defines Leff(weak) > Lg. Optimal straggle and extension length define best SCE (Ioff) vs. RS/D (Ion) tradeoff; further, Vt can be adjusted for different applications via controlled S/D dopants in channel, with reasonable sensitivity to process variations. Lg=18nm, Lext=30nm, wSi=12nm Leff(weak) Leff(strong) ≅ Lg

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Very high mobilities can be achieved in undoped FinFETs.

Low transverse electric field (⇐ Qi/2) yields high carrier mobilities: UFDG calibrations to long-Lg FinFETs

nMOSFETs ⇒ electron mobilities pMOSFETs ⇒ hole mobilities

µn(eff) [cm2/V-s] Ninv [1013cm-2]

{110} DG nFinFET - UFDG {100} bulk nMOSFET - measured {100} DG nMOSFET - measured

0.5 1.0 1.5 2.0 100.0 150.0 200.0 250.0 300.0 350.0 400.0 450.0

µ0 = 565cm2/V-s θ = 0.20

≅x2

(wSi = 26nm)

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0.0 50.0 100.0 150.0 200.0 250.0

µp(eff) [cm2/V-s] Ninv [1013cm-2]

{110} DG pFinFET - measured {100} DG pMOSFET - measured {100} bulk pMOSFET - measured

{110} DG pFinFET - UFDG

{110} bulk pMOSFET - measured

µ0 = 250cm2/V-s θ = 0.10

≅x3

(wSi = 30nm)

(low NB)

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But ....

Scaling Lg degrades µeff, which implies excessive scattering centers near the source/drain,

• r perhaps significant remote S/D Coulomb scattering.

Recent work suggests that this problem can be resolved via optimal S/D engineering. UFDG calibrations to nFinFETs with varying Lg

5.0e+12 1.0e+13 1.5e+13 2.0e+13 2.5e+13 80 130 180 230 280 330

Lg=1µm: UO=585, Θ=0.32 Lg=75nm: UO=400, Θ=0.2 Lg=32nm: UO=125, Θ=0.2 µn(eff) (cm2/V-s) Ninv (cm-2)

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UFDG/Spice3: Pragmatic nanoscale DG-FinFET CMOS can give good speed performance (with very low Ioff).

*The underlap and the thicker tox reduce the parasitic G-S/D fringe capacitance, which is very significant in nanoscale CMOS devices.

Lg = 18nm DG CMOS unloaded RO delays

0.7 0.8 0.9 1.0 1.1

VDD [V]

2.0 3.0 4.0 5.0 6.0 7.0 8.0

Abrupt NSD(y) w/ G-S/D overlap (0.1Lg) G-S/D underlap (3.4nm); tox = 1.0nm

32% speed improvement

G-S/D underlap (3.4nm); tox = 1.5nm

with pragmatic FinFET design*

Delay/Stage [ps]

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Conclusions

❋ Pragmatic nanoscale DG-FinFET CMOS is viable, and is potentially scalable to the end of the SIA ITRS (where Lg < 10nm). ❋ Source/drain engineering for G-S/D underlap, Vt adjustment, and high carrier mobilities must be

• ptimized; and tall, thin fins must be controlled.

❋ Further, SOI enables embedded FBC (e.g., 1T) DRAM, which can be viable.

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UFDG: A Process/Physics-Based Predictive Compact Model Applicable to Generic UTB DG MOSFETs

n+ Source n+ Drain Gate n+ Source n+ Drain Gate Wg = hSi tSi = wSi Lg

n+ n+ p ΦGf D S Gf Gb ΦGb

Leff tSi Wg UFDG is applicable to SG FD/ SOI MOSFETs, as well as symmetrical-, asymmetrical-, and independent-gate DG MOSFETs, including FinFETs. Gf = Gb

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Short-Channel Effects Modeling in UFDG

(or, how two gates give good control of the electrostatics) 2-D Poisson equation (for weak inversion), , is solved in (rectangular) body/channel (UTB) region, defined by tSi and Leff ≠ Lg, by assuming in Poisson, and applying the (four) boundary conditions (including surface-state charge at both interfaces). The derived potential (with QM shift) defines the integrated (in x-y, over tSi) inversion charge (Qi) and an effective channel length (Le < Leff averaged over tSi) for predominant diffusion current (in y), and thus accounts for:

* S/D charge (impurity and/or carrier) sharing [Vt(Leff) & S(Leff)] , * DIBL (throughout UTB) [∆Vt(VDS)] .

∂2φ ∂x2

• ∂2φ

∂y

• +

qNB εSi

• ≅

φ x y , ( ) α0 y ( ) α1 y ( )x α2 y ( )x2 + + ≅

ΦGf Gf Gb

toxf

toxb ΦGb tSi UTB Leff

S D

y x

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Quantization Effects Modeling in UFDG

UFDG is actually a compact Poisson-Schrödinger solver:

1-D SWE analytical solution is derived using a variational approach, then coupled to PE and Qi(VGfS, VGbS) via Newton-Raphson iteration, all with dependence on tSi and Si

• rientation, as well as Ex.

n+ poly gates

Classical PE

(charge coupling, inversion-charge distribution) potentials,

SWE

(eigenfunctions, eigenvalues, 2-D DOS, F-D) updated potentials, electric fields electric fields

0.0 0.2 0.4 0.6 0.8 1.0 Normalized Position x/tSi 0.0 0.5 1.0 1.5 2.0 Eigenfunction Ψ0 (104 m-1/2) Model SCHRED VGS = 1.5V 1.0V 0.6V 1.5V tSi = 20nm tSi = 5nm

QM Qi & Ich

(classical Qi & Ich) SDG nMOSFETs: tox=1.5nm NB=1017cm-3 in UTB/channel The QM modeling is also the basis for a physical mobility model for the UTB carrier transport.