High aspect-ratio I nGaAs FinFETs with sub-20 nm fin width Alon - PowerPoint PPT Presentation

High aspect-ratio I nGaAs FinFETs with sub-20 nm fin width Alon Vardi, Jianqiang Lin, Wenjie Lu, Xin Zhao and Jesús A. del Alamo Microsystems Technology Laboratories, MIT June 15, 2016 Sponsors: DTRA (HDTRA 1-14-1-0057), NSF E3S STC (grant #0939514) Lam Research

Outline • Motivation • Process technology • Electrical characteristics • Late news • Conclusions 2

I nGaAs planar Quantum-Well MOSFETs MIT MOSFETs del Alamo, J-EDS 2016 • Superior electron transport properties in InGaAs • InGaAs planar MOSFET performance exceeds that of High Electron Mobility Transistors (HEMT) 3

I nGaAs planar Quantum-Well MOSFETs - short-channel effects t c =12 nm 400 350 S min (mV/dec) t c ↓ 300 250 V ds =0.5 V 200 150 3 nm 100 0.01 0.1 1 10 L g ( µ m) Lin, IEDM 2014 • Short-channel effects limit scaling to L g ~ 40 nm • 3D transistors required for further scaling 4

FinFETs Intel Si Trigate MOSFETs • FinFETs are use in modern state-of-the-art technologies • Good balance of SCE and high ON current per footprint 5

I nGaAs FinFETs W f ~50 nm W f ~30 nm Thathachary, VLSI 2015 Waldron, VLSI 2014 W f ~50 nm Kim, TED 2014 Radosavljevic ,IEDM 2011 Kim, IEDM 2013 • Demonstrations to date: W f ≥ 25 nm, AR c ≤ 1 6

Goal: Sub-20 nm W f Self-aligned I I I -V FinFETs High -K HSQ SiO 2 AR c = H c /W f L g W/Mo AR f = H f /W f cap W f channel H c H f InAlAs • Deeply scaled fin width, gate length and gate oxide • High channel to fin width aspect ratio (AR c ) • Self-aligned contacts • CMOS-compatible processes and materials in front- end 7

Fin definition: Dry etch + Digital etch 170 nm 25 nm 100 nm • BCl 3 /SiCl 4 /Ar RIE of InGaAs nanostructures with smooth, vertical sidewalls and high 8 nm aspect ratio (>10) • Digital etch (DE) : self-limiting O 2 plasma oxidation + H 2 SO 4 30 nm oxide removal 8

Device fabrication 30 nm In 0.53 Ga 0.47 As, Si doped 3e19 cm -3 4 nm InP stopper 40 nm In 0.53 Ga 0.47 As, undoped • Highly doped cap 5 nm In 0.52 Al 0.48 As • 40 nm thick channel layer Si δ -Doping: 4e12 cm -2 • Delta doping underneath In 0.52 Al 0.48 As buffer InP semi insulating substrate 9

Device fabrication W f direction L g direction Sputtered W/Mo contact o CVD SiO 2 hard mask SiO 2 o W/Mo cap channel InAlAs 10

Device fabrication L g direction Sputtered W/Mo contact W f direction o CVD SiO 2 hard mask o SiO 2 35 nm L g Gate lithography o W/Mo Gate recess (Dry): o cap SiO 2 /W/Mo SiO 2 channel Active area definition o W/Mo InAlAs 11

Device fabrication L g direction Sputtered W/Mo contact W f direction o CVD SiO 2 hard mask o SiO 2 35 nm L g Gate lithography o W/Mo Gate recess (Dry): o cap SiO 2 /W/Mo SiO 2 channel Active area definition o W/Mo Gate recess (Wet): Cap o etch InAlAs L g 60 nm SiO 2 W/Mo InP InGaAs 20 nm 12

Device fabrication HSQ Sputtered Mo contact o CVD SiO 2 hard mask o Gate lithography o Gate recess (Dry): o H c SiO 2 /W/Mo H f Active area definition o Gate recess (Wet): Cap 100 nm o etch Fin Lithography o Fin etch o 13

Device fabrication HSQ Sputtered W/Mo contact o CVD SiO 2 hard mask o Gate lithography o Gate recess (Dry): o H c SiO 2 /W/Mo H f Active area definition o 100 nm Gate recess (Wet): Cap o etch Fin lithography o Fin etch o Mo Digital etching o High-k/Mo ALD gate dielectric o HSQ deposition Mo gate sputtering 20 nm o • Double gate FinFET 14 • Al 2 O 3 /HfO 2 , EOT = 1 nm

Device fabrication Sputtered W/Mo contact o CVD SiO 2 hard mask o Gate lithography o Gate recess (Dry): o SiO 2 /W/Mo Active area definition o Gate recess (Wet): Cap o etch Via Fin Lithography o Fin etch o SiO 2 Digital etching o ALD gate dielectric o deposition Gate hat Mo gate sputtering o Gate head photo and o pattern • Fin pitch 200 nm ILD1 deposition o Via opening o Pad formation o • 10-50 fins/device 15

Long channel characteristics, W f = 22 nm, L g = 2 μ m Al 2 O 3 /HfO 2 1E-4 V GS = 0.75 V 25 EOT = 1 nm V DS =500 mV 1E-5 20 50 mV 1E-6 15 I d [A/ µ m] I d [ µ A/ µ m] 1E-7 0.5 V 10 1E-8 S lin =68 mV/dec 5 DIBL~0 1E-9 0 V 0.25 V 1E-10 0 -0.2 0.0 0.2 0.4 0.6 0.8 0.0 0.1 0.2 0.3 0.4 0.5 V GS [V] V DS [V] • S lin =68 mV/dec • Negligible DIBL • Good electrostatic control over dry etched sidewalls 16

Short channel characteristics, W f = 22 nm, L g = 30 nm 1200 V GS = 0.75V 1000 1600 0.5 1000 800 1200 I d [ µ A /µ m] g m [ µ S /µ m ] 800 I d [ µ A /µ m] 600 0.25 600 800 400 V DS =500mV H c 400 0 400 200 W f =22 nm 200 -0.25 L g =30 nm 0 -0.5 0 0 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 0.0 0.2 0.4 0.6 0.8 1.0 V GS [V] V DS [V] 1E-3 V DS =500 mV Current normalized 1E-4 50 mV by 2xH c 1E-5 170 I d [A /µ m] DIBL=220 mV/V • AR c ~2 1E-6 S=140 mV/dec • g m,max = 1.4 mS/ µ m at W f =22 nm 1E-7 L g =30 nm V DS =0.5 V 1E-8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 • R on =170 Ω ∙ µ m V GS [V] 17

Most aggressively scaled device, W f = 7 nm, L g = 20 nm V GS = 0.75 V 40 V DS =500 mV W f =7 nm 1E-5 L g =20 nm 0.5 30 50 mV I d [ µ A /µ m] 1E-6 S=120 mV/dec I d [A /µ m] DIBL~150 20 1E-7 0.25 1E-8 10 0 -0.25 1E-9 0 1E-10 0.0 0.2 0.4 0.6 0.8 1.0 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 V DS [V] V GS [V] • AR c ~6 • Poor drive current  Increased line edge roughness for W f <10 nm 18

L g and W f scaling g m,max at V DS =0.5 V 1600 1200 W f =22 nm 800 400 1600 0 1200 W f =17 nm 800 g m [ µ S/ µ m] 400 1600 0 1200 W f =12 nm 800 400 1600 0 W f =7 nm 1200 800 400 0 10 100 1000 L g [nm] • L g ↓  g m ↑ • W f ↓  g m ↓ 19

L g and W f scaling S sat at V DS =0.5 V g m,max at V DS =0.5 V 200 1600 W f =22 nm 150 1200 W f =22 nm 100 800 400 50 1600 0 200 0 W f =17 nm 1200 W f =17 nm 150 800 g m [ µ S/ µ m] 400 100 S sat [mV/dec] 1600 0 50 1200 W f =12 nm 200 0 800 W f =12 nm 400 150 1600 0 100 W f =7 nm 1200 50 800 400 200 0 W f =7 nm 0 150 10 100 1000 L g [nm] 100 50 • L g ↓  g m ↑ 0 10 100 1000 • W f ↓  g m ↓ L g [nm] • W f ↓  L g @ onset of SCE ↓ 20

L g and W f scaling I on at I off =100 nA/ μ m g m,max at v DS =0.5 V S sat at V DS =0.5 V c 200 1600 200 W f =22 nm W f =22 nm 150 1200 W f =22 nm 150 c 800 100 100 400 50 50 I off =100 nA/ µ m 1600 0 200 0 c 200 0 W f =17 nm W f =17 nm 1200 150 W f =17 nm 150 c 800 S min [mV/dec] 100 g m [ µ S/ µ m] 400 50 100 I on [ µ A/ µ m] 1600 0 200 0 50 W f =12 nm 1200 W f =12 nm 150 200 0 c 800 100 W f =12 nm 150 400 50 c 1600 0 200 0 100 W f =7 nm W f =7 nm 1200 150 50 800 100 50 0 400 50 W f =7 nm 40 0 0 10 100 1000 30 10 100 1000 L g [nm] L g [nm] 20 10 • L g ↓  g m ↑ 0 10 100 1000 L g [nm] • W f ↓  g m ↓ • W f ↓  L g @ max I on ↓ • W f ↓  L g @ onset of SCE ↓ 21

ON resistance scaling 4000 W f =7 nm 3500 3000 12 R on [ Ω - µ m] 2500 2000 17 1500 1000 22 500 0 0 100 200 300 400 500 L g [nm] • W f ↓  R on ↑ • For all W f , R sd =100 Ω ∙ µ m • Extremely low series resistance due to contact first and self-aligned approach 22

V T rolloff 0.8 0.6 0.4 V T [V] 0.2 0.0 -0.2 -0.4 W f =7 nm W f =12 nm W f =22 nm W f =17 nm 0 400 800 0 400 800 0 400 800 0 400 800 L g [nm] • W f ↓  V T ↑  delta doping, quantization • W f ↓  V T rolloff ↑  line edge roughness ? A. Vardi, IEDM 2015 23

Benchmark Physical g m : W F normalized by gate periphery 2.0 0.18 Si FinFETs H c 5.3 0.23 0.66 4.3 1.5 1 0.57 g m [mS/ µ m] 1.0 0.63 0.6 0.8 0.5 InGaAs FinFETs 0.0 0 20 40 60 H C W f [nm] W f • g m of Si ~ g m of III-V • III-V FinFET AR c ≤ 1 24

Benchmark Physical g m : W F normalized by gate periphery 2.0 0.18 Si FinFETs H c 5.3 0.23 0.66 4.3 1.5 1 0.57 g m [mS/ µ m] 1.8 MIT 2.3 InGaAs 1.0 FinFETs 0.63 3.3 0.6 0.8 0.5 5.7 InGaAs FinFETs 0.0 0 20 40 60 H C W f [nm] W f Our results: • AR c >1 for the first time in III-V • Sub-20 nm W f • W f ↓  g m ↓ 25

Benchmark Footprint g m : Physical g m : normalized by fin width 2.0 20 0.18 Si FinFETs 5.3 W f 5.3 0.23 0.66 Si FinFETs 4.3 1.5 15 4.3 1 g m /W f [mS/ µ m] 0.57 g m [mS/ µ m] 1.8 MIT 2.3 InGaAs 1.0 10 FinFETs InGaAs FinFETs 0.63 3.3 3.3 0.6 0.5 0.8 5 1 0.66 2.31.8 5.7 0.18 0.23 5.7 InGaAs FinFETs 0.57 0.63 0.6 0.8 0.0 0 0 20 40 60 0 20 40 60 W f [nm] W f [nm] For g m /W f : • Si >> III-V • MIT FinFETs > all other III-V  good use of sidewall conductance  Our results improve the state-of-art 26

Post-submission results V DS =500 mV V GS =-0.5 to 0.75 -4 500 10 Δ V GS = 0.25 V 50 mV I d 400 -6 10 S=100 mV/dec I d [ µ A/ µ m] I [A/ µ m] 300 DIBL=90 mV/V -8 10 200 -10 10 I g 100 -12 10 0 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0 0.1 0.2 0.3 0.4 0.5 V GS [V] V DS [V] 1000 g m max =0.9 mS/ μ m 800 V DS =500 mV W f =7 nm g m [ µ S/ µ m] 600 L g =30 nm 400 50 mV EOT=0.6 nm (HfO 2 ) 200 0 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 V GS [V] 27