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High aspect-ratio I nGaAs FinFETs with sub-20 nm fin width Alon Vardi, Jianqiang Lin, Wenjie Lu, Xin Zhao and Jess A. del Alamo Microsystems Technology Laboratories, MIT June 15, 2016 Sponsors: DTRA (HDTRA 1-14-1-0057), NSF E3S STC (grant

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SLIDE 1

High aspect-ratio I nGaAs FinFETs with sub-20 nm fin width

Alon Vardi, Jianqiang Lin, Wenjie Lu, Xin Zhao and Jesús A. del Alamo

Microsystems Technology Laboratories, MIT June 15, 2016

Sponsors: DTRA (HDTRA 1-14-1-0057), NSF E3S STC (grant #0939514) Lam Research

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SLIDE 2

Outline

  • Motivation
  • Process technology
  • Electrical characteristics
  • Late news
  • Conclusions

2

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SLIDE 3

I nGaAs planar Quantum-Well MOSFETs

  • Superior electron transport properties in InGaAs
  • InGaAs planar MOSFET performance exceeds that
  • f High Electron Mobility Transistors (HEMT)

3

MIT MOSFETs del Alamo, J-EDS 2016

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SLIDE 4

I nGaAs planar Quantum-Well MOSFETs - short-channel effects

  • Short-channel effects limit scaling to Lg~40 nm
  • 3D transistors required for further scaling

4

Lin, IEDM 2014

0.01 0.1 1 10 100 150 200 250 300 350 400

Smin (mV/dec)

Lg(µm)

Vds=0.5 V

tc ↓ tc=12 nm 3 nm

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SLIDE 5

5

Intel Si Trigate MOSFETs

FinFETs

  • FinFETs are use in modern state-of-the-art technologies
  • Good balance of SCE and high ON current per footprint
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SLIDE 6

6

I nGaAs FinFETs

Radosavljevic ,IEDM 2011 Kim, IEDM 2013

  • Demonstrations to date: Wf ≥ 25 nm, ARc ≤ 1

Kim, TED 2014 Thathachary, VLSI 2015 Waldron, VLSI 2014 Wf~30 nm Wf~50 nm Wf~50 nm

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SLIDE 7

Goal: Sub-20 nm Wf Self-aligned I I I -V FinFETs

  • Deeply scaled fin width, gate length and gate oxide
  • High channel to fin width aspect ratio (ARc)
  • Self-aligned contacts
  • CMOS-compatible processes and materials in front-

end

7

InAlAs channel cap W/Mo Lg SiO2 HSQ High -K

Hc Wf

ARc = Hc/Wf ARf = Hf/Wf Hf

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SLIDE 8

Fin definition: Dry etch + Digital etch

8

30 nm 100 nm

8 nm 170 nm

  • BCl3/SiCl4/Ar RIE of InGaAs

nanostructures with smooth, vertical sidewalls and high aspect ratio (>10)

  • Digital etch (DE): self-limiting

O2 plasma oxidation + H2SO4

  • xide removal

25 nm

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SLIDE 9

Device fabrication

9

30 nm In0.53Ga0.47As, Si doped 3e19 cm-3 4 nm InP stopper 40 nm In0.53Ga0.47As, undoped 5 nm In0.52Al0.48As Si δ-Doping: 4e12 cm-2 In0.52Al0.48As buffer InP semi insulating substrate

  • Highly doped cap
  • 40 nm thick channel layer
  • Delta doping underneath
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SLIDE 10

Device fabrication

10

Wf direction Lg direction InAlAs channel cap W/Mo SiO2

  • Sputtered W/Mo contact
  • CVD SiO2 hard mask
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SLIDE 11

Device fabrication

11

35 nm SiO2 W/Mo Wf direction Lg direction InAlAs channel cap W/Mo SiO2 Lg

  • Sputtered W/Mo contact
  • CVD SiO2 hard mask
  • Gate lithography
  • Gate recess (Dry):

SiO2/W/Mo

  • Active area definition
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SLIDE 12

Device fabrication

12

35 nm SiO2 W/Mo

InP W/Mo SiO2 20 nm InGaAs 60 nm

Wf direction Lg direction InAlAs channel cap W/Mo SiO2 Lg Lg

  • Sputtered W/Mo contact
  • CVD SiO2 hard mask
  • Gate lithography
  • Gate recess (Dry):

SiO2/W/Mo

  • Active area definition
  • Gate recess (Wet): Cap

etch

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SLIDE 13

13

HSQ Hc Hf 100 nm

Device fabrication

  • Sputtered Mo contact
  • CVD SiO2 hard mask
  • Gate lithography
  • Gate recess (Dry):

SiO2/W/Mo

  • Active area definition
  • Gate recess (Wet): Cap

etch

  • Fin Lithography
  • Fin etch
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SLIDE 14

14

HSQ Hc Hf High-k/Mo 100 nm

20 nm

Device fabrication

  • Sputtered W/Mo contact
  • CVD SiO2 hard mask
  • Gate lithography
  • Gate recess (Dry):

SiO2/W/Mo

  • Active area definition
  • Gate recess (Wet): Cap

etch

  • Fin lithography
  • Fin etch
  • Digital etching
  • ALD gate dielectric

deposition

  • Mo gate sputtering

Mo HSQ

  • Double gate FinFET
  • Al2O3/HfO2 , EOT = 1 nm
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SLIDE 15

15

Via SiO2

Gate hat

Device fabrication

  • Sputtered W/Mo contact
  • CVD SiO2 hard mask
  • Gate lithography
  • Gate recess (Dry):

SiO2/W/Mo

  • Active area definition
  • Gate recess (Wet): Cap

etch

  • Fin Lithography
  • Fin etch
  • Digital etching
  • ALD gate dielectric

deposition

  • Mo gate sputtering
  • Gate head photo and

pattern

  • ILD1 deposition
  • Via opening
  • Pad formation
  • Fin pitch 200 nm
  • 10-50 fins/device
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SLIDE 16

Long channel characteristics, Wf= 22 nm, Lg= 2 μm

16

  • Slin=68 mV/dec
  • Negligible DIBL
  • Good electrostatic control over dry etched sidewalls

0.0 0.1 0.2 0.3 0.4 0.5 5 10 15 20 25 0 V 0.25 V 0.5 V Id [µA/µm] VDS [V] VGS= 0.75 V

  • 0.2

0.0 0.2 0.4 0.6 0.8 1E-10 1E-9 1E-8 1E-7 1E-6 1E-5 1E-4 DIBL~0 50 mV Id [A/µm] VGS [V] Slin=68 mV/dec VDS=500 mV

Al2O3/HfO2 EOT = 1 nm

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SLIDE 17

17

  • 0.6 -0.4 -0.2

0.0 0.2 0.4 0.6 0.8 200 400 600 800 1000 Wf=22 nm Lg=30 nm VDS=500mV

VGS [V] Id [µA/µm]

400 800 1200 1600

gm [µS/µm] 0.0 0.2 0.4 0.6 0.8 1.0 200 400 600 800 1000 1200

VGS= 0.75V 0.5 0.25

  • 0.25

Id [µA/µm] VDS [V]

  • 0.5
  • 0.6
  • 0.4
  • 0.2

0.0 0.2 0.4 0.6 1E-8 1E-7 1E-6 1E-5 1E-4 1E-3 DIBL=220 mV/V

VGS [V] Id [A/µm]

Wf=22 nm Lg=30 nm VDS=500 mV 50 mV S=140 mV/dec 170

  • ARc~2
  • gm,max = 1.4 mS/µm at

VDS=0.5 V

  • Ron=170 Ω∙µm

Short channel characteristics, Wf= 22 nm, Lg= 30 nm

Hc

Current normalized by 2xHc

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SLIDE 18

18

  • 0.6
  • 0.4
  • 0.2

0.0 0.2 0.4 0.6 1E-10 1E-9 1E-8 1E-7 1E-6 1E-5 Wf=7 nm Lg=20 nm VDS=500 mV

VGS [V] Id [A/µm]

50 mV S=120 mV/dec DIBL~150

0.0 0.2 0.4 0.6 0.8 1.0 10 20 30 40 VGS= 0.75 V 0.5 0.25

  • 0.25

Id [µA/µm] VDS [V]

  • ARc~6
  • Poor drive current  Increased line edge

roughness for Wf<10 nm

Most aggressively scaled device, Wf= 7 nm, Lg= 20 nm

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SLIDE 19

Lg and Wf scaling

19

10 100 1000

400 800 1200 1600 400 800 1200 1600 400 800 1200 1600 400 800 1200 1600

Lg [nm]

Wf=7 nm Wf=12 nm

gm [µS/µm]

Wf=17 nm Wf=22 nm

  • Lg ↓  gm ↑
  • Wf ↓  gm ↓

gm,max at VDS=0.5 V

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SLIDE 20

Lg and Wf scaling

20

10 100 1000 50 100 150 200 50 100 150 200 50 100 150 200 50 100 150 200

Lg [nm]

Ssat [mV/dec]

Wf=7 nm Wf=12 nm Wf=17 nm Wf=22 nm

gm,max at VDS=0.5 V

10 100 1000

400 800 1200 1600 400 800 1200 1600 400 800 1200 1600 400 800 1200 1600

Lg [nm]

Wf=7 nm Wf=12 nm

gm [µS/µm]

Wf=17 nm Wf=22 nm

Ssat at VDS=0.5 V

  • Lg ↓  gm ↑
  • Wf ↓  gm ↓
  • Wf ↓  Lg @ onset of SCE↓
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SLIDE 21

Lg and Wf scaling

21

10 100 1000 50 100 150 200 50 100 150 200 50 100 150 200 50 100 150 200

Lg [nm]

Smin [mV/dec]

Wf=7 nm Wf=12 nm Wf=17 nm Wf=22 nm

gm,max at vDS=0.5 V

10 100 1000

400 800 1200 1600 400 800 1200 1600 400 800 1200 1600 400 800 1200 1600

Lg [nm]

Wf=7 nm Wf=12 nm

gm [µS/µm]

Wf=17 nm Wf=22 nm

Ssat at VDS=0.5 V

  • Lg ↓  gm ↑
  • Wf ↓  gm ↓
  • Wf ↓  Lg @ onset of SCE ↓

10 100 1000 10 20 30 40 50 50 100 150 200 50 100 150 200 50 100 150 200 Lg [nm] Ion [µA/µm]

Ioff=100 nA/µm Wf=7 nm Wf=12 nm Wf=17 nm Wf=22 nm

c c c c c c

  • Wf ↓  Lg @ max Ion ↓

Ion at Ioff=100 nA/μm

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SLIDE 22

22

100 200 300 400 500 500 1000 1500 2000 2500 3000 3500 4000 12 22 17 Ron [Ω-µm] Lg [nm] Wf=7 nm

ON resistance scaling

  • Wf ↓  Ron↑
  • For all Wf , Rsd=100 Ω∙µm
  • Extremely low series resistance due to contact first and

self-aligned approach

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SLIDE 23

VT rolloff

23

400 800

  • 0.4
  • 0.2

0.0 0.2 0.4 0.6 0.8 Wf=12 nm VT [V] Wf=7 nm 400 800 Wf=22 nm Wf=17 nm Lg [nm] 400 800 400 800

  • Wf ↓  VT ↑  delta doping, quantization
  • Wf ↓  VT rolloff ↑  line edge roughness ?
  • A. Vardi, IEDM 2015
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SLIDE 24

Benchmark

24

Physical gm: normalized by gate periphery

HC

Wf

  • gm of Si ~ gm of III-V
  • III-V FinFET ARc≤1

Hc WF

20 40 60 0.0 0.5 1.0 1.5 2.0

0.8 0.57

InGaAs FinFETs

5.3 4.3

Si FinFETs

gm[mS/µm] Wf [nm]

0.63 0.6 0.23 0.66 1 0.18

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SLIDE 25

Benchmark

25

Physical gm: normalized by gate periphery

HC

Wf

Hc WF

20 40 60 0.0 0.5 1.0 1.5 2.0

0.8 0.57 5.7 3.3 2.3 1.8

InGaAs FinFETs

5.3 4.3

Si FinFETs

gm[mS/µm] Wf [nm]

0.63 0.6 0.23 0.66 1 0.18

MIT InGaAs FinFETs

  • ARc>1 for the first time in III-V
  • Sub-20 nm Wf
  • Wf ↓  gm ↓

Our results:

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SLIDE 26

Benchmark

26

20 40 60 5 10 15 20

0.57 0.8 5.7 3.3 2.31.8

InGaAs FinFETs

5.3 4.3

Si FinFETs

gm/Wf [mS/µm] Wf [nm]

0.63 0.6 0.23 0.66 1 0.18

  • Si >> III-V
  • MIT FinFETs > all other III-V

 good use of sidewall conductance  Our results improve the state-of-art Physical gm: Footprint gm: normalized by fin width

20 40 60 0.0 0.5 1.0 1.5 2.0

0.8 0.57 5.7 3.3 2.3 1.8

InGaAs FinFETs

5.3 4.3

Si FinFETs

gm[mS/µm] Wf [nm]

0.63 0.6 0.23 0.66 1 0.18

MIT InGaAs FinFETs

Wf

For gm/Wf:

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SLIDE 27

27

  • 0.4
  • 0.3
  • 0.2
  • 0.1

0.1 0.2 200 400 600 800 1000 VGS [V] gm [µS/µm]

  • 0.4
  • 0.3
  • 0.2
  • 0.1

0.1 0.2 10

  • 12

10

  • 10

10

  • 8

10

  • 6

10

  • 4

VGS [V] I [A/µm] 0.1 0.2 0.3 0.4 0.5 100 200 300 400 500 VDS [V] Id [µA/µm]

Wf=7 nm Lg=30 nm EOT=0.6 nm (HfO2)

VGS=-0.5 to 0.75 ΔVGS=0.25 V

gm max=0.9 mS/μm

S=100 mV/dec

Id Ig

DIBL=90 mV/V

Post-submission results

VDS=500 mV 50 mV VDS=500 mV 50 mV

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SLIDE 28

Benchmark with latest results

28

20 40 60 5 10 15 20

EOT=1 nm (HfO2/Al2O3) EOT=0.6 nm (HfO2) 0.57 0.8 5.7 3.32.31.8

InGaAs FinFETs

5.3 4.3

Si FinFETs

gm/Wf [mS/µm] Wf [nm]

0.63 0.6 0.23 0.66 1 0.18

20 40 60 0.0 0.5 1.0 1.5 2.0

0.8 0.57 5.7 3.3 2.3 1.8

InGaAs FinFETs

5.3 4.3

Si FinFETs

gm[mS/µm] Wf [nm]

0.63 0.6 0.23 0.66 1 0.18

Physical gm: Footprint gm:

  • New record results for sub-10 nm Wf InGaAs FinFETs
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SLIDE 29

Conclusions

29

  • Novel self-aligned gate-last FinFET:

– Self-aligned gate to contact metals – CMOS process compatibility – Sub-10 nm fin width – ARc>1 for the first time in III-V – Double-gate FinFET

  • Outstanding performance and short-channel effects

in devices with Lg=30 nm and Wf=22 nm

  • Demonstrated subthreshold swing of 68 mV/dec in

long channel devices

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SLIDE 30

Thank you !

30