Self-Aligned InGaAs FinFETs with 5-nm Fin-Width and 5-nm - - PowerPoint PPT Presentation

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Self-Aligned InGaAs FinFETs with 5-nm Fin-Width and 5-nm Gate-Contact Separation Alon Vardi, Lisa Kong, Wenjie Lu, Xiaowei Cai, Xin Zhao, Jess Grajal* and Jess A. del Alamo Microsystems Technology Laboratories, Massachusetts Institute of

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SLIDE 1

Self-Aligned InGaAs FinFETs with 5-nm Fin-Width and 5-nm Gate-Contact Separation

Alon Vardi, Lisa Kong, Wenjie Lu, Xiaowei Cai, Xin Zhao, Jesús Grajal* and Jesús A. del Alamo

Microsystems Technology Laboratories, Massachusetts Institute of Technology, Cambridge, MA, U.S.A *ETSI Telecomunicación, Universidad Politécnica de Madrid, Madrid, Spain

  • Dec. 5, 2017

Sponsors: DTRA (HDTRA 1‐14‐1‐0057) NSF E3S STC (grant #0939514) Lam Research Korea Institute of Science and Technology

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SLIDE 2

Intel Si Trigate MOSFETs

FinFETs

FinFETs used in state‐of‐the‐art Si CMOS

  • improved short‐channel effects
  • smaller footprint
  • but… higher parasitics

Double gate Tri gate

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SLIDE 3

10 20 30 Planar 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

Si FinFETs

gm[mS/m] Wf [nm]

Si and InGaAs FinFETs

normalized by gate periphery

//

  • Si planar  FinFET: performance ↓

22 nm 14 nm Planar Si 32 nm

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SLIDE 4

10 20 30 Planar 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

Si FinFETs

gm[mS/m] Wf [nm] 10 20 30 Planar 5 10 15 20

5.3 4.3

Si FinFETs (VDD=0.8 V)

gm/Wf [mS/m] Wf [nm]

Si and InGaAs FinFETs

  • Si planar  FinFET: performance ↓, performance per footprint ↑
  • Key challenge for FinFETs  efficient transport on sidewalls

normalized by fin footprint

Wf Hc

AR=Hc/Wf

// //

normalized by gate periphery

22 nm 14 nm Planar Si 32 nm

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SLIDE 5

10 20 30 Planar 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

Si FinFETs

gm[mS/m] Wf [nm] 10 20 30 Planar 5 10 15 20

5.3 4.3

Si FinFETs (VDD=0.8 V)

gm/Wf [mS/m] Wf [nm]

Si and InGaAs FinFETs

normalized by fin footprint

Wf Hc

AR=Hc/Wf

// //

normalized by gate periphery

  • III‐V planar ~ Si planar

Planar InGaAs (VDD=0.5 V) Lin, EDL2016

22 nm 14 nm Planar Si 32 nm

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SLIDE 6

10 20 30 Planar 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

Si FinFETs

gm[mS/m] Wf [nm]

Planar InGaAs (VDD=0.5 V) Lin, EDL2016

10 20 30 Planar 5 10 15 20

5.7

InGaAs FinFETs

5.3 4.3

Si FinFETs (VDD=0.8 V)

gm/Wf [mS/m] Wf [nm] 10 20 30 Planar 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

Si FinFETs

gm[mS/m] Wf [nm]

Si and InGaAs FinFETs

normalized by fin footprint

Wf Hc

// //

normalized by gate periphery

  • gm(III‐V FinFETs) < gm(Si)
  • Target of Wf=5 nm yet to be demonstrated

22 nm 14 nm Planar Si 32 nm

Target: WF=5 nm

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SLIDE 7

10 20 30 Planar 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5

InGaAs FinFETs Si FinFETs

gm[mS/m] Wf [nm] 10 20 30 Planar 5 10 15 20

5.7

InGaAs FinFETs

5.3 4.3

Si FinFETs (VDD=0.8 V)

gm/Wf [mS/m] Wf [nm]

Si and InGaAs FinFETs

normalized by fin footprint

Wf Hc

// //

normalized by gate periphery

  • III‐V FinFET: Wf< 20 nm  gm ↓
  • Challenge: Improve III‐V sidewall conductivity

Planar InGaAs (VDD=0.5 V) Lin, EDL2016

22 nm 14 nm Planar Si 32 nm

Target: WF=5 nm

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SLIDE 8

MIT InGaAs FinFET’s Gen. #2 vs. #1

Mo InAlAs cap Mo/W SiO2 Lg InGaAs channel HfO2 HSQ Mo InAlAs cap Mo/W SiO2 InGaAs channel Lf,g Lf

Gen #2:

  • Dry cap recess
  • 5 Digital etch cycles
  • 50 nm channel
  • Fin‐top passivation
  • Remove δ‐doping (in 2nd stage)
  • Gen. #1: Vardi et al., VLSI 2016, EDL 2016
  • Gen. #2: This work

InP Mo/W SiO2 InGaAs 60 nm

40nm Channel Cap Mo/W SiO2 Wet recess Dry+DE recess ~5 nm ~20 nm

Gen #1:

  • Wet cap recess
  • 3 Digital etch cycles
  • 40 nm channel height
  • δ‐doping

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SLIDE 9

Process Technology: contact-first

InGaAs cap Mo/W SiO2 InGaAs channel InAlAs InP stopper ‐Doping

  • Yield RC < 10 Ω∙µm

Lin, IEDM 2013 Lu, EDL 2014 Vardi, EDL 2014 Lg direction W direction Contact deposition

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SLIDE 10

InGaAs cap Mo/W InGaAs channel Lg direction InAlAs InP stopper ‐Doping

Dry+Digital Etch cap recess

  • No metal pullback
  • III‐V cap pullback only during digital etch

Lg Lf Reactive ion etching Digital etching (Lin, IEDM 2013) Contact etch W direction

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40nm Channel Cap Mo/W SiO2 Dry+DE recess ~5 nm

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SLIDE 11

Dry+Digital Etch fin definition

100 nm

8 nm 170 nm

  • BCl3/SiCl4/Ar RIE + 5 DE cycles : smooth, vertical sidewalls and high aspect ratio (>10)

Zhao, EDL 2014, Vardi, VLSI 2016 Fin HSQ HSQ Wf direction Lg direction InAlAs cap Mo/W SiO2 Hc Hf Lg Wf InGaAs channel Fin etch

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Cap recess fin

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SLIDE 12

Gate stack - Double gate FinFET

  • HSQ stays on top of fins

 double‐gate FinFET

  • Gate oxide – 3 nm HfO2

(vs. 2.3 nm in EDL2016)

HSQ Mo Hc Hf Lg Wf Top fin passivation HfO2 HSQ Gate stack InGaAs cap Mo/W SiO2 InGaAs channel InAlAs ‐Doping Lg direction W direction

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InP stopper Fin etch Cap recess Contact deposition fin

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SLIDE 13

Device cross section

5 nm

  • Fin pitch: 200 nm
  • 10‐200 fins/device
  • Wf : 5‐25 nm
  • Lg : 30 nm – 5 µm
  • Contact to channel separation set by DE : ~5 nm

TEM of finished device in Wf direction FIB cross section in Lg direction

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SLIDE 14
  • 0.2

0.0 0.2 0.4 0.6 0.8 1E-9 1E-8 1E-7 1E-6 1E-5 1E-4 1E-3 50 mV VDS=500 mV Id [A/m] VGS [V] Lg=50 nm Wf=5 nm

  • 0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0

100 200 300 400 500 600 700 gm [S/m] VGS [V] VDS=0.5 V Lg=50 nm Wf=5 nm 0.0 0.1 0.2 0.3 0.4 0.5 50 100 150 200 250 Id [A/m] VGS [V]

VGS=-0.2 to 0.5 V VGS=0.1 V

Electrical characteristics: Wf=5 nm, Lg=50 nm

  • Well behaved devices with Wf=5 nm

Ssat=100 mV/dec Slin=73 mV/dec

gm,max=600 µS/µm Normalized by gate periphery

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SLIDE 15

5 10 15 20 25 0.0 0.5 1.0 1.5 2.0 gm[mS/m] Wf [nm] 5 10 15 20 25 60 120 180 Ssat [mV/dec] Wf [nm]

On/Off performance: fin width scaling

  • Wf ↓: Ssat ↓
  • Wf ↓: gm ↓

Lg=40‐60 nm Lg=40‐60 nm VDS = 0.5 V VDS = 0.5 V

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SLIDE 16

To improve Off performance: remove δ-doping

Mo InAlAs cap Mo SiO2 InGaAs cap HSQ fin Extrinsic area

  • δ‐doping  Rsd ↓
  • Dry gate recess allows to remove δ‐doping
  • Impact on the intrinsic fin transport
  • Gen. #1
  • Gen. #2 ‐ δ‐doped

Mo cap Mo SiO2 InGaAs cap HSQ

  • Gen. #2 ‐ Undoped

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‐Doping

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SLIDE 17
  • 0.2

0.0 0.2 0.4 0.6 0.8 1E-9 1E-8 1E-7 1E-6 1E-5 1E-4 1E-3 50 mV VDS=500 mV Id [A/m] VGS [V] Lg=50 nm Wf=5 nm

  • 0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0

100 200 300 400 500 600 700  doped undoped gm [S/m] VGS [V] VDS=0.5 V Lg=50 nm Wf=5 nm 0.0 0.1 0.2 0.3 0.4 0.5 50 100 150 200 250 Id [A/m] VGS [V]

VGS=-0.2 to 0.5 V VGS=0.1 V

WF=5 nm FinFET: Electrical characteristics: δ-doped vs. undoped

  • better OFF performance
  • Undoped Similar ON performance

Normalized by gate periphery

Ssat=100 mV/dec Slin=73 mV/dec Ssat=75 mV/dec Slin=65 mV/dec

gm,max=600 µS/µm gm,max=500 µS/µm

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Undoped fins:

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SLIDE 18

5 10 15 20 25 0.0 0.5 1.0 1.5 2.0 Undoped -doped gm[mS/m] Wf [nm] 5 10 15 20 25 60 120 180 Undoped -doped Ssat [mV/dec] Wf [nm]

  • Undoped fin: improved electrostatics
  • For Wf<20 nm undoped‐fin ON performance also better

Lg=40‐60 nm Lg=40‐60 nm

Electrical characteristics: δ-doped vs. undoped

VDS = 0.5 V

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SLIDE 19

Undoped fins smaller variation of VT with WF  Improved VT rolloff

Electrical characteristics: VT rolloff

200 400 600

  • 0.2
  • 0.1

0.0 0.1 0.2 0.3 0.4 0.5 VT,lin [V] Lg [nm]

Undoped

200 400 600

  • 0.2
  • 0.1

0.0 0.1 0.2 0.3 0.4 0.5

Wf=5 nm Wf=9 Wf=13 Wf=17 Wf=21 Wf=25

VT,lin [V] Lg [nm]

δ‐doped

WF ↓ WF ↓

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SLIDE 20

10 20 30 40 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 Undoped -doped

InGaAs FinFETs Si FinFETs

gm[mS/m] Wf [nm]

Benchmarking

normalized by gate periphery

  • Systematic gm degradation for Wf < 15 nm for both δ‐doped and undoped structures
  • No improvement from increased #DE cycles
  • Higher EOT  lower gm w.r.t. to Gen. 1

Hc Hc

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SLIDE 21

Benchmarking

normalized by gate periphery

Wf

  • Record Wf with good electrical performance
  • Approaching Si FinFETs even at VDD=0.5 V
  • Record AR=10

5 10 20 30 40 5 10 15 20 Undoped -doped

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InGaAs FinFETs

5.3 4.3

Si FinFETs (VDD=0.8 V)

gm/Wf [mS/m] Wf [nm]

Hc Hc

Target: WF=5 nm 10 20 30 40 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 Undoped -doped

InGaAs FinFETs Si FinFETs

gm[mS/m] Wf [nm]

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SLIDE 22

Long-channel Mobility vs. Wf

  • Strong µ degradation as Wf ↓
  • Wf < 10 nm  µ independent of nl

Capacitance measured @ 1GHz Wf=25 nm Wf=9 nm δ‐doped undoped

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SLIDE 23

Simulations – charge distribution

ON state: nl=3x107 cm‐1

y

Wf=25 nm undoped δ‐doped

  • Undoped fin: better use of sidewalls
  • δ‐doped fin: conduction close to lower facet of channel

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SLIDE 24

Simulations – charge distribution

ON state: nl=3x107 cm‐1

y

Wf=9 nm Wf=25 nm undoped δ‐doped undoped δ‐doped

  • Narrow fin: volume inversion in both δ‐doped and undoped fins

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SLIDE 25

Simulations – capacitance

undoped δ‐doped

ON state: nl=3x107 cm‐1 (VGT~0.4V)

y

Es(y)

undoped δ‐doped Wf=9 nm Wf=25 nm undoped δ‐doped undoped δ‐doped

Simulation

  • Reasonable agreement between measurement and simulations

 extract nl ‐ Es relation

Simulation Simulation Simulation

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SLIDE 26

Wf=25 nm Wf=9 nm δ‐doped undoped Wf=25 nm Wf=9 nm δ‐doped undoped

  • Wide fin: ES (δ‐doped) < ES (undoped)
  • Narrow fin: ES (δ‐doped) ~ ES (undoped)

Simulations – Mobility vs. Field

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Body conductance

At similar nl :

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SLIDE 27

Long-channel Mobility vs. Wf

  • Large over drive: µ(δ‐doped) ~ µ(undoped)
  • Strong µ degradation as Wf ↓
  • Wf < 10 nm  µ saturate

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nl = 3x107 cm‐1 VGT ~ 0.4 V nl = 3x107 cm‐1 VGT ~ 0.4 V

5 10 15 20 25 500 1000 1500

-doped

 [cm

2/Vsec]

Wf [nm]

5 10 15 20 25 500 1000 1500  [cm

2/Vsec]

Wf [nm]

Undoped

δ‐doped Undoped

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SLIDE 28
  • Self-aligned gate-last InGaAs FinFET:

– Self-aligned gate and contact trough precision RIE and digital etch – Record AR=10

  • Record Wf =5 nm InGaAs FinFET with good electrical performance
  • Performance enhancement in narrow fins via δ-doping removal

Conclusions Thank you !

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