Nanoscale III-V Electronics: InGaAs FinFETs and Vertical Nanowire - - PowerPoint PPT Presentation

Nanoscale III-V Electronics: InGaAs FinFETs and Vertical Nanowire MOSFETs

• J. A. del Alamo, X. Zhao, W. Lu, A. Vardi and X. Cai

Microsystems Technology Laboratories

Massachusetts Institute of Technology

IEEE Nanotechnology Materials and Devices Conference Portland, OR, October 14-17, 2018 Acknowledgements:

• Students and collaborators: D. Antoniadis, E. Fitzgerald, J. Grajal, J. Lin
• Sponsors: Applied Materials, DTRA, Intel, KIST, Lam Research, Northrop

Grumman, NSF, Samsung, SRC

• Labs at MIT: MTL, EBL

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Evolution of transistor structure for improved scalability

Planar bulk MOSFET Thin-body SOI MOSFET Nanowire MOSFET

Enhanced gate control  improved scalability

FinFET

Moore’s Law: The Problem

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Scaling: Voltage ↓  Current density ↓  Performance ↓ Current density of n-MOSFETs at nominal voltage:

III-V CMOS: The Promise

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del Alamo, Nature 2011

Source injection velocity: Si vs. InGaAs vinj(InGaAs) > 2vinj(Si) at less than half VDD  high current at low voltage

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Evolution of transistor structure for improved scalability

Planar bulk MOSFET Thin-body SOI MOSFET Nanowire MOSFET

Enhanced gate control  improved scalability

FinFET Thin-body MOSFET

n-MOSFETs in Intel’s nodes at nominal voltage

Transconductance of Planar Si vs. InGaAs MOSFETs

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“Comparisons always fraught with danger…”

n-MOSFETs in Intel’s nodes at nominal voltage

Transconductance of Planar Si vs. InGaAs MOSFETs

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• InGaAs stagnant for a long time

n-MOSFETs in Intel’s nodes at nominal voltage

Transconductance of Planar Si vs. InGaAs MOSFETs

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• Rapid recent progress  Atomic Layer Deposition
• InGaAs exceeds Si

n-MOSFETs in Intel’s nodes at nominal voltage

Transconductance of Planar Si vs. InGaAs MOSFETs

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MIT (VDS=0.5 V)

Lin, IEDM 2014, EDL 2016

• Rapid recent progress  Atomic Layer Deposition
• InGaAs exceeds Si

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Evolution of transistor structure for improved scalability

Planar bulk MOSFET Thin-body SOI MOSFET Nanowire MOSFET

Enhanced gate control  improved scalability

FinFET FinFET

Transconductance of planar Si vs. InGaAs MOSFETs

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Transconductance of Si vs. InGaAs FinFETs

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Transconductance of Si vs. InGaAs FinFETs

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gm normalized by fin width

Wf FinFET: large increase in current density per unit footprint over planar MOSFET

Transconductance of Si vs. InGaAs FinFETs

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Best InGaAs FinFETs nearly match 14 nm Si MOSFETs

MIT (VDS=0.5 V)

gm normalized by fin width

Wf

Transconductance of Si vs. InGaAs FinFETs

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10 nm node Si MOSFETs: a great new challenge!

10 nm node Intel (VDS=0.7 V)

gm normalized by fin width

Wf

MIT (VDS=0.5 V)

InGaAs FinFETs @ MIT

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Vardi, DRC 2014, EDL 2015, IEDM 2015

Key enabling technologies: BCl3/SiCl4/Ar RIE + digital etch

• Sub-10 nm fin width
• Aspect ratio > 20
• Vertical sidewalls

InGaAs FinFETs @ MIT

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Vardi, IEDM 2017

• Si-compatible process
• Contact-first, gate-last process
• Fin etch mask left in place  double-gate MOSFET

InAlAs InGaAs

n+-InGaAs

W/Mo Lg SiO2 HSQ High-K InP δ - Si InP Mo Mo HSQ High-K InGaAs

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Most aggressively scaled FinFET

Wf=5 nm, Lg=50 nm, Hc=50 nm (AR=10), EOT=0.8 nm:

Vardi, IEDM 2017

• 0.2

0.0 0.2 0.4 0.6 0.8 1E-9 1E-8 1E-7 1E-6 1E-5 1E-4 1E-3

Ssat=75 mV/dec Slin=65 mV/dec

50 mV VDS=500 mV Id [A/m] VGS [V] Lg=50 nm Wf=5 nm 0.0 0.1 0.2 0.3 0.4 0.5 50 100 150 Id [A/m] VGS [V]

VGS=-0.2 to 0.5 V VGS=0.1 V

gm,max=565 µS/µm (VDS=0.5 V)

Normalized by conducting gate periphery = 2Hc

5 10 15 20 25 40 60 80 100 120 Ssat Slin S [mV/dec] Wf [nm]

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• Excellent subthreshold swing scaling behavior
• From long Lg devices: Dit ~ 8x1011 cm-2.eV-1

Vardi, IEDM 2017

Slin (VDS = 50 mV) Ssat (VDS = 0.5 V) Lg=40-60 nm

• 0.2

0.0 0.2 0.4 0.6 0.8 1E-9 1E-8 1E-7 1E-6 1E-5 1E-4 1E-3

Ssat=75 mV/dec Slin=65 mV/dec

50 mV VDS=500 mV Id [A/m] VGS [V] Lg=50 nm Wf=5 nm

Wf scaling of OFF-state characteristics

5 10 15 20 25 200 400 600 800 1000 Ron[-m] Wf [nm]

5 10 15 20 25 0.0 0.5 1.0 1.5 2.0 gm[mS/m] Wf [nm]

Wf scaling of ON-state characteristics

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• gm independent of Wf down

to Wf=7 nm

• In planar MOSFET (x=0.53)

expect gm~ 2.2 mS/µm

• Missing performance hints

at sidewall damage

Vardi, IEDM 2017 in planar MOSFETs expect 2.2 mS/µm

Lg=40-60 nm VDS = 0.5 V Normalized by conducting gate periphery = 2Hc

DC underestimates transistor potential!

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gm frequency dispersion Pulsed vs. DC

• Severe frequency dispersion in gm
• Pulsed I-V ≠ DC I-V
• Due to gate oxide trapping

Cai, CSW 2018

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Planar bulk MOSFET Thin-body SOI MOSFET Nanowire MOSFET FinFET VNW MOSFET

InGaAs Vertical Nanowire MOSFETs

Vertical NW MOSFET:  ultimate scalable transistor  uncouples footprint scaling from Lg, Lspacer, and Lc scaling

InGaAs Vertical Nanowires on Si by direct growth

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Selective-Area Epitaxy (SAE) InAs NWs on Si by SAE Riel, MRS Bull 2014, IEDM 2012

VNW MOSFETs: path for III-V integration on Si for future CMOS

NMOS PMOS

InGaAs VNWs by top-down approach

Key enabling technologies: BCl3/SiCl4/Ar RIE + digital etch DE = O2 plasma oxidation + acid-based oxide removal

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Zhao, EDL 2014 RIE + 5 cycles DE Radial etch rate = 1 nm/cycle

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10% HCl in DI water, Yield = 0%

Broken NWs

8 nm InGaAs VNWs after 7 DE cycles: Lu, EDL 2017 RIE down to D~20 nm + multiple cycles of DE

Towards D<10 nm InGaAs VNWs

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10% HCl in DI water, Yield = 0%

Broken NWs

8 nm InGaAs VNWs after 7 DE cycles: Lu, EDL 2017 Water-based acid is problem:

Surface tension (mN/m):

• Water: 72
• Methanol: 22
• IPA: 23

Solution: alcohol-based digital etch RIE down to D~20 nm + multiple cycles of DE

Towards D<10 nm InGaAs VNWs

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10% HCl in IPA, Yield = 97% 10% HCl in DI water, Yield = 0%

Alcohol-based DE key for D < 10 nm

Broken NWs

8 nm InGaAs VNWs after 7 DE cycles: Lu, EDL 2017 RIE down to D~20 nm + multiple cycles of DE

Towards D<10 nm InGaAs VNWs

D=5.5 nm InGaAs VNW arrays

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90% yield

10% H2SO4 in methanol

• H2SO4:methanol yields 90% at D=5.5 nm!
• Viscosity matters: methanol (0.54 cP) vs. IPA (2.0 cP)

Lu, EDL 2017

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Aspect Ratio > 40

D=5 nm InGaAs VNW

Lu, EDL 2017

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InGaAs VNW-MOSFETs by top-down approach @ MIT

Zhao, IEDM 2017

Top-down approach: flexible and manufacturable

III-V VNW MOSFET process flow

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also Ni

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D=7 nm InGaAs VNW MOSFET (Ni contact)

Zhao, IEDM 2017, TED 2018

• 0.2

0.0 0.2 0.4 0.6 10

• 9

10

• 8

10

• 7

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• 6

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• 5

10

• 4

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• 3

D = 7 nm

Slin/Ssat = 85/90 mV/dec DIBL = 222 mV/dec Vds=0.5 V Vgs(V) Id (A/m) Vds=0.05 V

0.0 0.1 0.2 0.3 0.4 0.5 100 200 300 400 500 600 700 800 Id (A/m)

Vgs= 0 V to 0.8 V in 0.1 V step D = 7 nm

Vds (V) 0.0 0.1 0.2 0.3 0.4 0.5 20 40 60 80 100 Vgs= 0 V to 0.8 V in 0.1 V step D = 7 nm Top contact = Source Vds (V) Id (A/m)

Source down Source up

• Single nanowire MOSFET (Lch= 80

nm)

• First sub-10 nm diameter VNW FET
• f any kind on any material system

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Output characteristics

• vs. D (source up)

As D↓:

• Ni contact becomes

Schottky

• Mo contact opens

up Source up: Ni top contact Mo top contact

Zhao, TED 2018

Sidewall MOS interface quality

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Subthreshold swing vs. electrostatic aspect ratio of channel:

Zhao, TED 2018

Poor MOS interface at sidewall Dit ~ 6x1012 cm-2.eV-1 (200oC RTA)

(ideal)

Dit ~ 4x1012 cm-2.eV-1 (300oC RTA)

60 160 260 400 800 1200 1600 2000 This work - Mo Vds=0.5 V

Ssat (mV/dec)

gm,pk (S/m)

Persson EDL 2010 Tomioka IEDM 2011 Tomioka Nature 2012 Persson DRC 2012 Berg IEDM 2015 Ramesh VLSI 2016, 0.4 V Kilpi VLSI 2017 Kilpi IEDM 2017 Ramesh IEDM 2017 Zhao IEDM 2013 This work - Mo This work - Ni

This work - Ni

Benchmark with Si/Ge VNW MOSFETs

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Excellent combination of on-and off-state characteristics Peak gm (VDS=0.5 V) vs. Ssat of InGaAs VNW MOSFETs

Zhao, IEDM 2017

5 10 15 20 25 30 35 40 400 800 1200 1600 2000 Target: D = 7 nm This work - Mo gm,pk (S/m)

Si/Ge, 1-1.2 V InGaAs This work - Mo This work - Ni

Diameter (nm) This work - Ni

Benchmark with Si/Ge VNW MOSFETs

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InGaAs competitive with Si [hard to add strain] Peak gm of InGaAs (VDS=0.5 V), Si and Ge VNW MOSFETs

Zhao, IEDM 2017

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InGaAs/InAs VNW Tunnel FETs @ MIT

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InGaAs VNW-TFET

0.0 0.1 0.2 0.3 0.4 0.5 0.0 0.5 1.0 1.5 2.0

Vgs=0 V to 0.6 V in 0.1 V step Vds (V)

Id (A/m)

• 0.4
• 0.2

0.0 0.2 0.4 10

• 6

10

• 5

10

• 4

10

• 3

10

• 2

10

• 1

10

Vgs= 0 V to 0.6 V in 0.1 V step Vds (V)

Id (A/m)

• Saturated output characteristics
• Clear negative differential resistance
• Peak to valley ratio of 3.4 @ Vgs = 0.6 V

Zhao, EDL 2017 Single NW: D= 40 nm, Lch= 60 nm, 3 nm Al2O3 (EOT = 1.5 nm)

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VNW-TFET subthreshold characteristics

0.0 0.1 0.2 0.3 0.4 0.5 10

• 11

10

• 10

10

• 9

10

• 8

10

• 7

10

• 6

10

• 5

0.0 0.1 0.2 0.3 0.4 0.5 5 10 15 20 Vgs(V) gm (S/m) Vd= 0.3 V

Vd=0.3 V Vgs(V) Id (A/m) Vd=0.05 V

• Sub-thermal for 2 orders of magnitude of current
• Slin = 55 mV/dec
• Ssat = 53 mV/dec

10

• 11

10

• 10

10

• 9

10

• 8

10

• 7

10

• 6

50 60 70 80 90 100 110 120 130 140 150

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• 10

10

• 9

50 55 60 Id (A/m) S (mV/dec) Vd = 0.3 V

S (mV/dec) Id (A/m)

Vd = 0.05 V Vd = 0.3 V

T=300 K

Zhao, EDL 2017

Conclusions

1. Great recent progress on planar, fin and nanowire InGaAs MOSFETs 2. Device performance still lacking for 3D architecture designs  severe oxide trapping masks true transistor potential 3. Vertical Nanowire MOSFET: ultimate scalable transistor; integrates well on Si

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NMOS PMOS