Nanoscale III-V Electronics: InGaAs FinFETs and Vertical Nanowire - PowerPoint PPT Presentation

Nanoscale III-V Electronics: InGaAs FinFETs and Vertical Nanowire MOSFETs J. A. del Alamo, X. Zhao, W. Lu, A. Vardi and X. Cai Microsystems Technology Laboratories Massachusetts Institute of Technology IEEE Nanotechnology Materials and Devices Conference Portland, OR, October 14-17, 2018 Acknowledgements: • Students and collaborators: D. Antoniadis, E. Fitzgerald, J. Grajal, J. Lin • Sponsors: Applied Materials, DTRA, Intel, KIST, Lam Research, Northrop Grumman, NSF, Samsung, SRC • Labs at MIT: MTL, EBL

Evolution of transistor structure for improved scalability Planar bulk Nanowire MOSFET MOSFET Thin-body SOI MOSFET FinFET Enhanced gate control  improved scalability 2

Moore’s Law: The Problem Current density of n-MOSFETs at nominal voltage: Scaling: Voltage ↓  Current density ↓  Performance ↓ 3

III-V CMOS: The Promise Source injection velocity: Si vs. InGaAs del Alamo, Nature 2011 v inj (InGaAs) > 2v inj (Si) at less than half V DD  high current at low voltage 4

Evolution of transistor structure for improved scalability Planar bulk Nanowire Thin-body MOSFET MOSFET MOSFET Thin-body SOI MOSFET FinFET Enhanced gate control  improved scalability 5

Transconductance of Planar Si vs. InGaAs MOSFETs n-MOSFETs in Intel’s nodes at nominal voltage “Comparisons always fraught with danger…” 6

Transconductance of Planar Si vs. InGaAs MOSFETs n-MOSFETs in Intel’s nodes at nominal voltage • InGaAs stagnant for a long time 7

Transconductance of Planar Si vs. InGaAs MOSFETs n-MOSFETs in Intel’s nodes at nominal voltage • Rapid recent progress  Atomic Layer Deposition • InGaAs exceeds Si 8

Transconductance of Planar Si vs. InGaAs MOSFETs n-MOSFETs in Intel’s nodes at nominal voltage MIT (V DS =0.5 V) Lin, IEDM 2014, EDL 2016 • Rapid recent progress  Atomic Layer Deposition • InGaAs exceeds Si 9

Evolution of transistor structure for improved scalability Planar bulk Nanowire MOSFET MOSFET FinFET Thin-body SOI MOSFET FinFET Enhanced gate control  improved scalability 10

Transconductance of planar Si vs. InGaAs MOSFETs 11

Transconductance of Si vs. InGaAs FinFETs 12

Transconductance of Si vs. InGaAs FinFETs W f g m normalized by fin width FinFET: large increase in current density per unit footprint over planar MOSFET 13

Transconductance of Si vs. InGaAs FinFETs W f MIT (V DS =0.5 V) g m normalized by fin width Best InGaAs FinFETs nearly match 14 nm Si MOSFETs 14

Transconductance of Si vs. InGaAs FinFETs 10 nm node Intel (V DS =0.7 V) W f MIT (V DS =0.5 V) g m normalized by fin width 10 nm node Si MOSFETs: a great new challenge! 15

InGaAs FinFETs @ MIT Key enabling technologies: BCl 3 /SiCl 4 /Ar RIE + digital etch Vardi, • Sub-10 nm fin width DRC 2014, • Aspect ratio > 20 EDL 2015, • Vertical sidewalls IEDM 2015 16

InGaAs FinFETs @ MIT Mo Mo High-K HSQ SiO 2 HSQ L g W/Mo High-K n + -InGaAs InP InGaAs InGaAs δ - Si InAlAs InP Vardi, IEDM 2017 • Si-compatible process • Contact-first, gate-last process • Fin etch mask left in place  double-gate MOSFET 17

Most aggressively scaled FinFET W f =5 nm, L g =50 nm, H c =50 nm (AR=10), EOT=0.8 nm: Normalized by conducting gate periphery = 2H c 1E-3 V GS =-0.2 to 0.5 V L g =50 nm V DS =500 mV 150  V GS =0.1 V W f =5 nm 1E-4 50 mV 1E-5 100 I d [  A/  m] I d [A/  m] 1E-6 S sat =75 mV/dec S lin =65 mV/dec 1E-7 50 1E-8 0 1E-9 0.0 0.1 0.2 0.3 0.4 0.5 -0.2 0.0 0.2 0.4 0.6 0.8 V GS [V] V GS [V] g m,max =565 µS/µm (V DS =0.5 V) Vardi, IEDM 2017 18

W f scaling of OFF-state characteristics S sat (V DS = 0.5 V) 120 S sat 1E-3 L g =50 nm V DS =500 mV S lin W f =5 nm 1E-4 50 mV 100 1E-5 S [mV/dec] I d [A/  m] 80 1E-6 S sat =75 mV/dec S lin (V DS = 50 mV) S lin =65 mV/dec 1E-7 60 1E-8 L g =40-60 nm 1E-9 -0.2 0.0 0.2 0.4 0.6 0.8 40 0 5 10 15 20 25 V GS [V] W f [nm] • Excellent subthreshold swing scaling behavior • From long L g devices: D it ~ 8x10 11 cm -2 .eV -1 Vardi, IEDM 2017 19

W f scaling of ON-state characteristics 2.0 Vardi, IEDM 2017 1.5 g m [mS/  m] in planar 1.0 MOSFETs expect L g =40-60 nm 2.2 mS/µm 0.5 V DS = 0.5 V 0.0 0 5 10 15 20 25 W f [nm] Normalized by conducting 1000 gate periphery = 2H c 800 • g m independent of W f down 600 R on [  -  m] to W f =7 nm • In planar MOSFET (x=0.53) 400 expect g m ~ 2.2 mS/µm 200 • Missing performance hints 0 0 5 10 15 20 25 at sidewall damage W f [nm] 20

DC underestimates transistor potential! g m frequency dispersion Pulsed vs. DC Cai, CSW 2018 • Severe frequency dispersion in g m • Pulsed I-V ≠ DC I-V • Due to gate oxide trapping 21

InGaAs Vertical Nanowire MOSFETs Planar bulk Nanowire MOSFET MOSFET VNW MOSFET Thin-body SOI MOSFET FinFET Vertical NW MOSFET:  ultimate scalable transistor  uncouples footprint scaling from L g , L spacer , and L c scaling 22

InGaAs Vertical Nanowires on Si by direct growth Selective-Area Epitaxy InAs NWs on Si by SAE (SAE) Riel, MRS Bull 2014, IEDM 2012 NMOS PMOS VNW MOSFETs: path for III-V integration on Si for future CMOS 23

InGaAs VNWs by top-down approach Key enabling technologies: BCl 3 /SiCl 4 /Ar RIE + digital etch DE = O 2 plasma oxidation + acid-based oxide removal + 5 cycles DE RIE Zhao, EDL 2014 Radial etch rate = 1 nm/cycle 24

Towards D<10 nm InGaAs VNWs RIE down to D~20 nm + multiple cycles of DE Lu, EDL 2017 8 nm InGaAs VNWs after 7 DE cycles: Broken NWs 10% HCl in DI water, Yield = 0% 25

Towards D<10 nm InGaAs VNWs RIE down to D~20 nm + multiple cycles of DE Lu, EDL 2017 8 nm InGaAs VNWs after 7 DE cycles: Water-based acid is problem: Broken NWs Surface tension (mN/m): • Water: 72 • Methanol: 22 • IPA: 23 10% HCl in DI water, Yield = 0% Solution: alcohol-based digital etch 26

Towards D<10 nm InGaAs VNWs RIE down to D~20 nm + multiple cycles of DE Lu, EDL 2017 8 nm InGaAs VNWs after 7 DE cycles: Broken NWs 10% HCl in DI water, Yield = 0% 10% HCl in IPA, Yield = 97% Alcohol-based DE key for D < 10 nm 27

D=5.5 nm InGaAs VNW arrays 10% H 2 SO 4 in methanol 90% yield Lu, EDL 2017 • H 2 SO 4 :methanol yields 90% at D=5.5 nm! • Viscosity matters: methanol (0.54 cP) vs. IPA (2.0 cP) 28

D=5 nm InGaAs VNW Aspect Ratio > 40 Lu, EDL 2017 29

InGaAs VNW-MOSFETs by top-down approach @ MIT Zhao, IEDM 2017 Top-down approach: flexible and manufacturable 30

III-V VNW MOSFET process flow also Ni 31

D=7 nm InGaAs VNW MOSFET (Ni contact) 800 V gs = 0 V to 0.8 V in 0.1 V step -3 V ds =0.5 V 10 D = 7 nm 700 D = 7 nm -4 10 600 -5 10 V ds =0.05 V I d ( A/  m) 500 I d ( A/  m ) -6 10 400 300 -7 10 S lin /S sat = 85/90 mV/dec 200 -8 10 DIBL = 222 mV/dec 100 -9 10 0 -0.2 0.0 0.2 0.4 0.6 0.0 0.1 0.2 0.3 0.4 0.5 V gs (V) V ds (V) Source down 100 V gs = 0 V to 0.8 V in 0.1 V step D = 7 nm Source up 80 Top contact = Source I d ( A/  m) 60 • Single nanowire MOSFET (L ch = 80 40 nm) • First sub-10 nm diameter VNW FET 20 of any kind on any material system 0 0.0 0.1 0.2 0.3 0.4 0.5 V ds (V) Zhao, IEDM 2017, TED 2018 32

Ni top contact Mo top contact Output characteristics vs. D (source up) Source up: As D↓: • Ni contact becomes Schottky • Mo contact opens up Zhao, TED 2018 33

Sidewall MOS interface quality Subthreshold swing vs. electrostatic aspect ratio of channel: (ideal) Zhao, TED 2018 D it ~ 6x10 12 cm -2 .eV -1 (200 o C RTA) D it ~ 4x10 12 cm -2 .eV -1 (300 o C RTA) Poor MOS interface at sidewall 34

Benchmark with Si/Ge VNW MOSFETs Peak g m (V DS =0.5 V) vs. S sat of InGaAs VNW MOSFETs 2000 Persson EDL 2010 Tomioka IEDM 2011 Tomioka Nature 2012 This work - Ni Persson DRC 2012 1600 Berg IEDM 2015 Ramesh VLSI 2016, 0.4 V g m,pk (  S/  m ) Kilpi VLSI 2017 1200 Kilpi IEDM 2017 Ramesh IEDM 2017 Zhao IEDM 2013 This work - Mo 800 This work - Mo This work - Ni 400 V ds =0.5 V Zhao, IEDM 2017 0 60 160 260 S sat (mV/dec) Excellent combination of on-and off-state characteristics 35

Benchmark with Si/Ge VNW MOSFETs Peak g m of InGaAs (V DS =0.5 V), Si and Ge VNW MOSFETs Si/Ge, 1-1.2 V 2000 InGaAs Target: D = 7 nm This work - Mo This work - Ni This work - Ni 1600 g m,pk (  S/  m) 1200 800 This work - Mo 400 0 Zhao, IEDM 2017 5 10 15 20 25 30 35 40 Diameter (nm) InGaAs competitive with Si [hard to add strain] 36

InGaAs/InAs VNW Tunnel FETs @ MIT 37

InGaAs VNW-TFET Single NW: D= 40 nm, L ch = 60 nm, 3 nm Al 2 O 3 (EOT = 1.5 nm) V gs = 0 V to 0.6 V in 0.1 V step 2.0 0 10 V gs =0 V to 0.6 V in 0.1 V step -1 10 1.5 -2 10 I d ( A/  m) I d ( A/  m) 1.0 -3 10 -4 10 0.5 -5 10 -6 0.0 10 -0.4 -0.2 0.0 0.2 0.4 0.0 0.1 0.2 0.3 0.4 0.5 V ds (V) V ds (V) • Saturated output characteristics • Clear negative differential resistance • Peak to valley ratio of 3.4 @ V gs = 0.6 V Zhao, EDL 2017 38