R&D for a monolithic pixel sensor based on 150 nm SOI CMOS - - PowerPoint PPT Presentation

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VCI2007 T. Tsuboyama, 21 Feb. 2007 1

R&D for a monolithic pixel sensor based

• n 150 nm SOI CMOS technology

11th Vienna Conference on Instrumentation 21 Feb. 2007

• T. Tsuboyama (KEK)

for the SOIPIX collaboration

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VCI2007 T. Tsuboyama, 21 Feb. 2007

Outline

Introduction 2005 designs and preliminary results 2006 designs Effect of radiation and back-gate voltage. Summary

2

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VCI2007 T. Tsuboyama, 21 Feb. 2007 3

SOIPIX collaboration

KEK: Y. Arai(*), M. Hazumi, Y. Ikegami, T. Kohriki, O. Tajima, S. Terada, T. Tsuboyama, Y. Unno, Y. Ushiroda JAXA: H. Ikeda Niigata Univ.: T. Kawasaki OKI Elec. Ind. Co.: K. Fukuda, H. Hayashi, J. Ida, H. Komatsubara, M. Ohno SLAC: Hiro Tajima Tokyo Institute of Technology: H. Ishino ,Y. Saegusa, T. Takahashi Tsukuba Univ.: K. Hara, H. Miyake, A.Mochizuki

• Univ. of Hawaii: Gary Varner, Elena Martin

(* contact person)

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VCI2007 T. Tsuboyama, 21 Feb. 2007 4

Pixel sensors

Hybrid pixel sensors

Proved in LHC experiments. MEDIPIX: Extended applications to material and biology imaging.

Monolithic pixel sensor

The radiation detector and readout electronics are integrated in a single wafer. Free from the difficulties in the bump-bonding technology. Thinning could reduce material significantly.

MAPS: Monolithic Active Pixel Sensor

Similar to commercial CMOS camera. Epitaxial layer is used as radiation detector.

SOI: Silicon on insulator

Pioneering work has been done by SUCIMA project. Independent R&D started in 2005 at KEK

MAPS SUCIMA SOI pixel

Pixel Sensor ASIC bump bonding

Hybrid

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VCI2007 T. Tsuboyama, 21 Feb. 2007 5

SOI CMOS technology

Structure:

Low-resistivity silicon layer (for MOSFET) Buried oxide layer (BOX) Silicon substrate (support wafer)

MOS FETs are isolated from the substrate and from each other.

Low stray capacitance: Faster operation No parasitic transistors: Latch-up free. Insensitive to charge induced in the substrate: Rate of “single event” effect is significantly reduced.

SOI wafer and process is becoming a standard technology in the semiconductor industry.

Si Substrate Gate MOS

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VCI2007 T. Tsuboyama, 21 Feb. 2007 5

SOI CMOS technology

Structure:

Low-resistivity silicon layer (for MOSFET) Buried oxide layer (BOX) Silicon substrate (support wafer)

MOS FETs are isolated from the substrate and from each other.

Low stray capacitance: Faster operation No parasitic transistors: Latch-up free. Insensitive to charge induced in the substrate: Rate of “single event” effect is significantly reduced.

SOI wafer and process is becoming a standard technology in the semiconductor industry.

Si Substrate Gate MOS BOX

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VCI2007 T. Tsuboyama, 21 Feb. 2007 6

1st metal 2nd metal 3rd metal MOSFET Buried oxide Gate

OKI 150 nm SOI CMOS process

http://www.okisemi.com/english/soi.htm

Process 0.15µm Fully-Depleted SOI CMOS process, 1 Poly, 5 Metal layers, MIM capacitor SOI wafer (SOITEC) Diameter: 150 mmφ, Top Si : Cz, ~18 Ω-cm, p-type, ~40 nm thick Buried Oxide: 200 nm thick Handle wafer: Cz>1k Ω-cm, 650 µm thick Backside Thinned to 350 µm, plated with Al (200 nm) after the semiconductor process.

Photo of 200-nm SOI 1 µm

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VCI2007 T. Tsuboyama, 21 Feb. 2007

Substrate contact

7

1st metal layer Box Implant region Plug SOI wafer

Sensor structure is made below BOX.

Remove the BOX layer where implant is necessary. Inject ions to form p+ or n+ regions. Fill back the aperture with SiO2. Make a via hole. Fill the hole with contact plug. Bias can be applied to substrate and thicker depletion region can be obtained. This procedure is compatible with normal CMOS process.

Signal induced in the wafer is processed with the CMOS circuit above the BOX. Merits Thinning can be applied. Standard and up-to-date SOI CMOS technology can be used.

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VCI2007 T. Tsuboyama, 21 Feb. 2007

Substrate contact

7

1st metal layer Box Implant region Plug SOI wafer

Sensor structure is made below BOX.

Remove the BOX layer where implant is necessary. Inject ions to form p+ or n+ regions. Fill back the aperture with SiO2. Make a via hole. Fill the hole with contact plug. Bias can be applied to substrate and thicker depletion region can be obtained. This procedure is compatible with normal CMOS process.

Signal induced in the wafer is processed with the CMOS circuit above the BOX. Merits Thinning can be applied. Standard and up-to-date SOI CMOS technology can be used.

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VCI2007 T. Tsuboyama, 21 Feb. 2007

Substrate contact

7

1st metal layer Box Implant region Plug SOI wafer

Sensor structure is made below BOX.

Remove the BOX layer where implant is necessary. Inject ions to form p+ or n+ regions. Fill back the aperture with SiO2. Make a via hole. Fill the hole with contact plug. Bias can be applied to substrate and thicker depletion region can be obtained. This procedure is compatible with normal CMOS process.

Signal induced in the wafer is processed with the CMOS circuit above the BOX. Merits Thinning can be applied. Standard and up-to-date SOI CMOS technology can be used.

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VCI2007 T. Tsuboyama, 21 Feb. 2007

Substrate contact

7

1st metal layer Box Implant region Plug SOI wafer SiO2

Sensor structure is made below BOX.

Remove the BOX layer where implant is necessary. Inject ions to form p+ or n+ regions. Fill back the aperture with SiO2. Make a via hole. Fill the hole with contact plug. Bias can be applied to substrate and thicker depletion region can be obtained. This procedure is compatible with normal CMOS process.

Signal induced in the wafer is processed with the CMOS circuit above the BOX. Merits Thinning can be applied. Standard and up-to-date SOI CMOS technology can be used.

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VCI2007 T. Tsuboyama, 21 Feb. 2007

Substrate contact

7

1st metal layer Box Implant region Plug SOI wafer SiO2

Sensor structure is made below BOX.

Remove the BOX layer where implant is necessary. Inject ions to form p+ or n+ regions. Fill back the aperture with SiO2. Make a via hole. Fill the hole with contact plug. Bias can be applied to substrate and thicker depletion region can be obtained. This procedure is compatible with normal CMOS process.

Signal induced in the wafer is processed with the CMOS circuit above the BOX. Merits Thinning can be applied. Standard and up-to-date SOI CMOS technology can be used.

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VCI2007 T. Tsuboyama, 21 Feb. 2007

Substrate contact

7

1st metal layer Box Implant region Plug SOI wafer SiO2

Sensor structure is made below BOX.

Remove the BOX layer where implant is necessary. Inject ions to form p+ or n+ regions. Fill back the aperture with SiO2. Make a via hole. Fill the hole with contact plug. Bias can be applied to substrate and thicker depletion region can be obtained. This procedure is compatible with normal CMOS process.

Signal induced in the wafer is processed with the CMOS circuit above the BOX. Merits Thinning can be applied. Standard and up-to-date SOI CMOS technology can be used.

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VCI2007 T. Tsuboyama, 21 Feb. 2007

Substrate contact

7

1st metal layer Box Implant region Plug SOI wafer SiO2

Sensor structure is made below BOX.

Remove the BOX layer where implant is necessary. Inject ions to form p+ or n+ regions. Fill back the aperture with SiO2. Make a via hole. Fill the hole with contact plug. Bias can be applied to substrate and thicker depletion region can be obtained. This procedure is compatible with normal CMOS process.

Signal induced in the wafer is processed with the CMOS circuit above the BOX. Merits Thinning can be applied. Standard and up-to-date SOI CMOS technology can be used.

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VCI2007 T. Tsuboyama, 21 Feb. 2007

Substrate contact

7

1st metal layer Box Implant region Plug SOI wafer SiO2 SiO2

Sensor structure is made below BOX.

Remove the BOX layer where implant is necessary. Inject ions to form p+ or n+ regions. Fill back the aperture with SiO2. Make a via hole. Fill the hole with contact plug. Bias can be applied to substrate and thicker depletion region can be obtained. This procedure is compatible with normal CMOS process.

Signal induced in the wafer is processed with the CMOS circuit above the BOX. Merits Thinning can be applied. Standard and up-to-date SOI CMOS technology can be used.

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VCI2007 T. Tsuboyama, 21 Feb. 2007 8

List of 2005 TEG

Name AMPTEG Preamp, Time over threshold, comparator, active feed back etc. RADTEG Pixel, transistor, ring oscillator PIXTEG 32x32 pixel array with readout STRIPTEG Short strip sensor HAWAIITEG Hard X-ray compton polarimeter

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VCI2007 T. Tsuboyama, 21 Feb. 2007 9

Strip TEG

DC coupled strips without active circuit is designed to measure basic characteristics of the sensor part. The 2.5 x 2.5 mm2 chip is divided into eight regions with different strip width. Breakdown voltage: ~50V.

Far less than the expected full depletion voltage (200 V). An infrared camera revealed the breakdown takes place at guard ring. Breakdown voltage could be improved by guard ring design.

The charge collection efficiency is not saturated at the breakdown voltage.

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VCI2007 T. Tsuboyama, 21 Feb. 2007 10

Laser Light injection window

Laser scan

Focused IR Laser (λ=980 nm) is injected from the top surface. Beam spot size ~ 10 um. There are windows for light injection. Reasonable charge collection, separation and share between strips are confirmed. When laser spot hits the readout metal traces, the

• bserved charge

decreases.

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VCI2007 T. Tsuboyama, 21 Feb. 2007 11

Pixel TEG

Purpose: demonstrate the potentiality of SOI as a pixel radiation sensor. 32x32 cells of 20x20 µm2 pixel matrix.

In each pixel, four octagonal implants (4x4 µm2) collects charge from the substrate. Breakdown voltage ~100V. Operation ~ 10 V to reduce back-gate effect.

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VCI2007 T. Tsuboyama, 21 Feb. 2007

Readout circuit.

Each channel is equipped with a circuit consists of 7 FETs.

Doubly correlated sampling, similar to readout circuit for MAPS.

12

Reset Integrate charge Readout Sample/Hold

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VCI2007 T. Tsuboyama, 21 Feb. 2007 13

Evaluation with laser light

“KEK06” image by a 670 nm laser light.

Graph: Readout channel is changed every 12 µsec then reset is given and go to the next channel. The ramp up speed depends on the light intensity. Fully illuminated cells saturate in 3 µsec. The slope is consistent with the light intensity and the calculated detector capacitance.

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VCI2007 T. Tsuboyama, 21 Feb. 2007 14

Observation ofβray signal

The pixel chip is irradiated with a 90Sr βray source. Output voltage of one channel is observed with oscilloscope. Observed voltage jump corresponding to a particle hit. The voltage step is consistent with charge from a MIP. =dE/dx(MIP) x depletion depth (44 um) x circuit response.

90Sr source

Pixel sensor

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VCI2007 T. Tsuboyama, 21 Feb. 2007

17 designs were submitted Dec. 2006

2006 TEG designs

15

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VCI2007 T. Tsuboyama, 21 Feb. 2007

List of submitted designs

16

CHIP Name Size (mm2) Category Designers VARPIXEL

2.4 x 2.4

Measurement

• H. Miyake (Osaka Univ. --> Tsukuba Univ.)

TOPPIXN

2.4 x 2.4

Pixel

• Y. Arai (KEK)

OKI0612

2.4 x 2.4

Measure

• H. Takahashi, K. Shimazoe, Fuiwara (Tokyo Univ.)

Achip

2.4 x 2.4

Pixle

• P. Denes (LBL)

OKI_TOP

2.4 x 2.4

Pixel

• G. Deptuch (FNAL (BNL))

ATEG

2.4 x 2.4

Circuit

• H. Ikeda (JAXA/ISAS)

BTEG

2.4 x 2.4

Circuit

• H. Ikeda (JAXA/ISAS)

CTEG

2.4 x 2.4

Circuit

• H. Ikeda (JAXA/ISAS)

isas_set0612

2.4 x 2.4

Measurement

• D. Kobayashi (JAXA/ISAS)

RADFET1

2.4 x 2.4

Measurement

• T. Tsuboyama (KEK)

HawaiiNSUBSTRATE

5.0 x 5.0

Pixel

• E. Martin G. Varner (Univ. of Hawaii)

detectorPOLY

5.0 x 5.0

Measurement

• T. Tsuboyama (KEK)

TOP_PIXELSTRIP

5.0 x 5.0

Strip

• Y. Ikegami (KEK)

TOP_8PREAMP

5.0 x 5.0

Circuit

• Y. Arai, Y. Ikegami (KEK)

TOPTEG2

5.0 x 5.0

Measurement

• Y. Arai (KEK)

TOPINTPIX

5.0 x 5.0

Pixel

• Y. Arai (KEK)

TOPCOUNT 10.2 x 10.2 Pixel

• Y. Arai (KEK)

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VCI2007 T. Tsuboyama, 21 Feb. 2007

Count-pixel

Array of 128x128 pixels Pixel size: 50x50 µm2. Chip size: 10x10 mm2. Active area: 6.4x6.4 mm2.

17

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VCI2007 T. Tsuboyama, 21 Feb. 2007

Y out Reset Select Csr X X out Write Data CSR 16-bit Counter 16 9 +Vdet Test in Vth-H Vth-L DDL

Count-pixel

18

Inspired by MEDIPIX2 readout chip. Target: X ray imaging. Each pixel is equipped with a shaping amplifier with leak current compensation. a window comparator. a 16-bit counter Count the number of hits entering the pixel. The counter is read out after an arbitrary integration period. Each pixel consists of ~600 FETs. Total 10 Mega FETs in a chip.

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VCI2007 T. Tsuboyama, 21 Feb. 2007

Strip-pixel

In ILC and B factory vertex detectors, reduction of material thickness per silicon layer is preferable. At large radius, the occupancy is not an issue. Thinned monolithic sensor is a solution. Adding signal from several pixels, a pseudo strip sensor can be made. As signal from a pixel is smaller than that from fully-depleted sensors, amplifier is integrated to each pixel.

19

Pixel +amp Pixel +amp Pixel +amp

sum buffer

Pixel +amp Pixel +amp Pixel +amp

sum buffer

Pixel +amp Pixel +amp Pixel +amp

sum buffer x0 x1 x2 sum buffer y0 sum buffer y1 sum buffer y2

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VCI2007 T. Tsuboyama, 21 Feb. 2007 20

Radiation damage and back-gate effect

Radiation damage in CMOS FET: Positive charge trapped in the

• xide layer results in the threshold

shift of the FET. 150-nm technology CMOS FETs are usually radiation hard. The gate-oxide is enough thin. SOI CMOS: BOX layer below FETs affects the threshold voltage. Back-gate effect: the electric potential of the substrate causes threshold shift.

Substrate BOX MOSFET SiO2 Gate 2.5 nm 200 nm

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Measurement with RADTEG

The Id-Vg curves:

Before irradiation After irradiation of 2x1013 proton/cm2 Substrate voltage is varied -30 to 0 V.

Threshold shift due to irradiation can be cured with the substrate voltage. Comparison with TCAD simulation.

NMOS_LowVt_L/W=0.15/300

• 2.00E-04

0.00E+00 2.00E-04 4.00E-04 6.00E-04 8.00E-04 1.00E-03 0.2 0.4 0.6 Vgs(V) Id(A)

float pre-irrad_backgate=0 backgate=-30 backgate=-20 backgate=-10

Vg (V) NMOS_LowVt,L/W=0.15/300 1.0 0.8 0.6 0.4 0.2 0.0 Id (mA)

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VCI2007 T. Tsuboyama, 21 Feb. 2007 22

TCAD simulation

Reduce risks, time and costs of silicon process.

Silvaco: ATHENA/ATLAS (2-dimensional) Enexss (Japan made, 3-dimensional)

Proceeding with careful comparison of two system.

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VCI2007 T. Tsuboyama, 21 Feb. 2007 23

Reduction of back gate effect

BOX

Bulk: n- (~700 Ω cm, 6 x 1012 cm-3) Bias ring: (5 µm wide P+, 1 x 1020 cm-3)

distance

(80, 5, 2 µm)

Backbias (0-100 V)

350µm 200 nm

Studied with Enexss TCAD Back gate effect can be reduced by guard ring in the substrate. The threshold voltage of FETs is calculated with a

guard ring at distance of 2, 5 and 80 µm.

At 2 µm, the threshold shift can be suppressed to 0.1 V at bias voltage of 100 V. Such structure is implemented in the 2006 designs.

Preliminary FET

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Summary

R&D activity of SOI pixel sensor started in 2005. Evaluation of 2005 design TEGs.

Observed signal from sensors as expected. Effects of charge accumulation in BOX and potential of support wafer. Behavior is understood quantitative with TCAD.

Example from 2006 TEG chips. Schedule of 2007: Evaluation of 2006 chips. Study of thinning. Autumn: Submission of 2007 designs.

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KEK detector technology project (2005-)

Several detector R&D groups are organized independent of the physics projects

Result should be applicable not only for particle physics but also various fields

Subgroups

Novel photo sensor /MPPC GEM/MPGD ASIC SOI pixel Liq, Xe calorimeter

http://rd.kek.jp/