Planar Pixel Sensor Production at CiS Planar Pixel Sensor Production - - PowerPoint PPT Presentation

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Planar Pixel Sensor Production at CiS Planar Pixel Sensor Production at CiS Anna Macchiolo - MPP Munich 009 g, 5 th June 20 Project aimed to explore the possible range of application in fluence (hence detector radii) for planar pixels

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SLIDE 1

Planar Pixel Sensor Production at CiS

009

Anna Macchiolo - MPP Munich

Planar Pixel Sensor Production at CiS

g, 5th June 20

Project aimed to explore the possible range of application in fluence (hence detector radii) for planar pixels sensors at SLHC

hop, Freiburg

detector radii) for planar pixels sensors at SLHC. Wafer layouts for the n-in-n and n-in-p batches have been submitted to CiS

RD50 Worksh

R&D areas to be covered by this project: Comparison of performances between n- and p-bulk pixels: yeald,

cchiolo, 14th R

p p p p y , reliability, radiation hardness Slim edges, increase of the fraction of active area Cost reduction

  • A. Mac

1 Cost reduction Vertical integration

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SLIDE 2

R&D for Planar Pixel Sensors for SLHC

009

Common RD50 production with the contribution of:

  • ATLAS groups participating in the Planar Pixel Sensor Project (coordinator C.

Goessling TU Dortmund) established in view of the Insertable B-Layer upgrade

g, 5th June 20

Goessling, TU Dortmund), established in view of the Insertable B-Layer upgrade and SLHC CMS pixel group at PSI

hop, Freiburg

Parallel productions of n-on-p pixel sensors on 6” wafers within the

ATLAS Planar Pixel Sensor Project :

  • HPK
  • rganized by the KEK group

RD50 Worksh

  • HPK, organized by the KEK group
  • MICRON, organized by the Liverpool group

Planar technology is a natural baseline for pixel upgrades:

cchiolo, 14th R

  • proven and reliable
  • recent data from the RD50 Collaboration indicate sufficient radiation hardness

even at b-layer fluences

  • A. Mac

2

thanks to using industrial standard processes, cost effective production of large pixel sensor areas is achievable

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SLIDE 3

Foreseen production parameters

009

Parallel production of n-in-p and n-in-n wafers with several common

test devices to achieve a full comparison between the two technologies

Production with CiS (Erfurt, Germany) on 4” wafers

g, 5th June 20

n-in-n batch ~10 Fz wafers ~ 10 MCz wafers Double sided process n-in-p batch ~ 34 Fz wafers ~ 6 MCz wafers Single sided process

hop, Freiburg

p g p Resistivity [KΩ.cm] Thickness

RD50 Worksh

FZ n-type 3.5-5.7 285 MCZ n-type 0.85-1 300

cchiolo, 14th R

FZ p-type > 10 285 MCZ p-type > 2 300

  • A. Mac

3

Inter-pixel isolation methods: homogenous p-spray and moderated p-

spray for both batches

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SLIDE 4

Wafer layout of the n-in-p batch

009

FE-I3 (present ATLAS ASIC) Single

Chip Modules (SCM) with variations of the GR structure and isolation schemes

g, 5th June 20

FE-I4: new ATLAS pixel

ASIC (for IBL and SLHC outer layers): pitch 50x250 μm2, 22,6 x 19,2 mm².

hop, Freiburg

, ,

CMS Module (16 chips) + 5

SCM same geometry as in th t CMS i

RD50 Worksh

the present CMS n-in-n sensors (design by T. Rohe).

80 μm pitch strips: 4

cchiolo, 14th R

sensors with the RD50 standard design (large inactive edge for cutting trials) and 2 with a MPP-HLL

  • A. Mac

4

design (AC coupled).

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SLIDE 5

Wafer layout of the n-in-n batch

009

20 different SCM FE-I3 versions (see

slides about slim edges). Included the design of n-in-p SCM with n-in-n design realized by the Dortmund group (T. Wittig)

g, 5th June 20

FE I4

4 hi M d l Included the design of n in p SCM with GR on the front side comparison to real p-bulk after type conversion

hop, Freiburg

FE-I4 4-chips Module:

Current ATLAS pixel guard ring design Proposed sensor for the I t bl b L (IBL)

RD50 Worksh

Insertable b-Layer (IBL): because of the length of the sensor it is possible to reach an inactive fraction of ~1.5% ( ith t hi li ) i th

cchiolo, 14th R

(without shingling) using the current guard ring design.

2 samples of FE-I4 SCM

  • A. Mac

5

RD50 design strip detectors adapted to n-in-n technology.

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SLIDE 6

ATLAS pixels: Isolation schemes (I)

009

Standard SCM dimensions , 1100 μm from cutting edge to guard rings

545 Moderated p-spray

Moderated p-spray: standard isolation scheme between pixels

g, 5th June 20

545 16 rings

isolation scheme between pixels adopted by the present n-in-n ATLAS and CMS sensors.

hop, Freiburg

An opening in the nitride layer determines an increase of the boron implanted dose in the central region

RD50 Worksh

Moderated p-spray

implanted dose in the central region between the strips.

cchiolo, 14th R

n+ n+

p spray nitride opening

  • A. Mac

6

p-spray

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SLIDE 7

ATLAS pixels: Isolation schemes (II)

009

Moderated p-spray 545 Moderated p-spray Homogenous p-spray Homogenous p-spray

g, 5th June 20

545 16 rings635 19 rings

hop, Freiburg RD50 Worksh

Implementation in the pixel design of the isolation scheme with homogenous p-spray : good performances observed in the pre-irradiation characterization of th MPP HLL thi i l d ti h thi i l ti th d

cchiolo, 14th R

the MPP-HLL thin pixel production where this isolation method was implemented (see M. Beimforde’s talk, this workshop). Effects of different p-spray implantation parameters simulated and tested ith CiS p t pe micro strip detectors irradiated ith X ra s isolation holds

  • A. Mac

7 with CiS p-type micro-strip detectors irradiated with X-rays: isolation holds after irradiation also for very low p-spray doses (~ 0.7x1012 cm-2) (M.Beimforde, 13th RD50 Workshop).

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SLIDE 8

Th d i d i d i th t CiS i l b i i i b d th

ATLAS p-type pixels: Guard Ring Design (I)

009

  • The guard-ring design used in the p-type CiS pixel submission is based on the
  • ne implemented in the MPI-HLL thin pixel production. Performances of these

sensors in terms of Vbreak are extremely good. Still some possible improvements suggested by the pre-irradiation characterization of these devices.

g, 5th June 20

  • Investigation of the breakdown location with PHEMOS: probe-station equipped

with a CCD camera to detect hot spots in the sensor. gg y p

hop, Freiburg

  • Structures with homogenous p-spray: breakdown in the GRs @ 425 V

RD50 Worksh cchiolo, 14th R

  • A. Mac

8

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SLIDE 9

ATLAS p-type pixels: Guard Ring Design (I)

Th d i d i d i th t CiS i l b i i i b d th

009

  • The guard-ring design used in the p-type CiS pixel submission is based on the
  • ne implemented in the MPI-HLL thin pixel production. Performances of these

sensors in terms of Vbreak are extremely good. Still some possible improvements suggested by the pre-irradiation characterization of these devices.

g, 5th June 20

  • Investigation of the breakdown location with PHEMOS: probe-station equipped

with a CCD camera to detect hot spots in the sensor.

  • Structures with moderated p-spray: breakdown in the GRs @ 585 V redesign

gg y p

hop, Freiburg

Structures with moderated p spray: breakdown in the GRs @ 585 V redesign

  • f the 4th and 5th rings for the CiS production

RD50 Worksh

  • The location of the hot spot in the

bottom left corner is probably linked

cchiolo, 14th R

with the direction of the small misalignments among the different layers

  • A. Mac

9

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SLIDE 10

CiS d i I f th t l h th i

ATLAS p-type pixels: Guard Ring Design (II)

009

1 CiS design: Increase of the metal overhang on the inner side of the 4th and 5th rings both for the moderated and homogenous p-spray versions

Thanks to Rainer Richter for discussions and suggestions

Rings #1 and #2 in the CiS

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1 2 3 1 2 3 SOI hom. p-spray

Rings #1 and #2 in the CiS design are wider but with the same inter-distances and

  • verhang structure as in the

SOI ones

hop, Freiburg

3 4 5 3 4 5 CIS hom. p-spray

RD50 Worksh

CIS hom. p spray 1 SOI mod. p-spray 1 CIS mod. p-spray

cchiolo, 14th R

2 3 4 2 3 4 5

  • A. Mac

10 5 5 6

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SLIDE 11

Area of R&D: Slim Edges for ATLAS SLHC Pixel Detector

009

545 Moderated p-spray Moderated p-spray

Outer staves in the SLHC ATLAS pixel detector will probably be double-

  • sided. In the inner layers of the pixel system (single-sided) it is strongly

desired to avoid shingling:

g, 5th June 20

545 16 rings

desired to avoid shingling:

  • deteriorates thermal performances
  • complicates stave design and add cost slim edges needed at least on

hop, Freiburg

two sides! Different methods explored to achieve a larger fraction of active area:

RD50 Worksh

p g

  • fewer guard rings (both n- and p-type)
  • instrument with pixels the area corresponding to the guard ring on the back-

side (n in n only)

cchiolo, 14th R

side (n-in-n only)

  • alternative dicing method with respect to sawing (laser and DRIE)
  • A. Mac

11

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SLIDE 12

Slim Edges: reduced guard ring structures n-in-p

009

545 Moderated p-spray Moderated p-spray

Design of slimmed guard-rings structures aided by simulation activities carried out by the ATLAS LAL-LAPNHE

g, 5th June 20

545 16 rings

y groups. Both in the n-in-n and n-in-p designs the slimmed edge versions have been

515 μm

hop, Freiburg

g implemented mostly in the FE-I3 sensors more variations are possible due to the reduced size with respect to the FE-I4 sensors

16 rings

RD50 Worksh

sensors

Encouraging results from the MPP-HLL

thin pixel production : p-type diodes with a reduced set of guard rings (10 guard

240 μm 8 i

cchiolo, 14th R

reduced set of guard rings (10 guard rings, homogenous p-spray) yield the same Vbreak (~ 400-500 V depending on p-spray dose) as those with the standard

8 rings

  • A. Mac

12 guard-ring structure.

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SLIDE 13

Slim Edges: reduced guard ring structures n-in-n (I)

009

545 Moderated p-spray Moderated p-spray

Current FE-I3 design where the number of guard-rings on the back-side is decreased to :

13

g, 5th June 20

545 16 rings

13 – 11 – 5 - 3

515 μm

hop, Freiburg

16 rings

RD50 Worksh cchiolo, 14th R

3

  • A. Mac

13

3

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SLIDE 14

Slim Edges: reduced guard ring structures n-in-n (II)

009

Samples with GRs shifted 100um and

11GR

~50um inactive area

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shifted 100um and 200um under the active area

100um

More extreme

hop, Freiburg

260um

More extreme configurations where the GRs number is reduced to 11 or 3 and

RD50 Worksh

shifted completely under the active area Investigation of

cchiolo, 14th R

g

  • field forming
  • Charge collection

Inactive area is reduced to ~50μm

  • A. Mac

efficiency (test beams)

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SLIDE 15

Slim Edges: dicing with DRIE

D RIE Alt ti di i th d t i ith l f d

009

Deep RIE : Alternative dicing method to sawing with less surface damage. Some wafers in the n- and p-batches will be dedicated to etching trials at CNM.

g, 5th June 20

Cutting lines implemented at a short distance from the end of the GR structure (30-40 μm).

hop, Freiburg

n+ p n-p

  • G. Pellegrini,

CNM

RD50 Worksh

Al

p+

Deep RIE to cut the wafer

cchiolo, 14th R

n+ n n-n

p+

  • A. Mac

15 Al Deep RIE to cut the wafer resist

p+

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SLIDE 16

R&D activities aimed at cost reduction

009

cc FC150 mark DataCon mark

Bare Module cost for ATLAS pixels:

Present

TU Dortmund + Bonn in collab. with IZM

g, 5th June 20

50µm cc 60µm

Present BB ~1900CHF IC ~1500CHF sensor ~550CHF hop, Freiburg

100µm 50µm µ

sum ~4000CHF

6” wafer and n-in-p single sided pixels should help to bring the sensor cost down

  • RD50 Worksh

Bare cost model favor larger chip size, less handling per unit area On the FE-I4 sensors new alignment marks were placed: Bump Bonding was the driving cost issue for the ATLAS pixel modules. 50 μm

pitch is today at the edge of cheap industrial solution

cchiolo, 14th R

On the FE-I4 sensors new alignment marks were placed:

Improve alignment speed and fault tolerance of the Suss FC150 machine -used for FE-I3 module prod.- better alignment marks. Add alignment marks for the new machine (DataCon 2200 apm) for faster pick-

  • A. Mac

16

Add alignment marks for the new machine (DataCon 2200 apm) for faster pick- and-place, but with lower accuracy. Minimum Specs are 80µm pitch and 40µm bump diameter not clear if 50µm pitch is possible!

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SLIDE 17

Pixel detectors for 3D technologies (I)

009

Several efforts within the ATLAS pixel community to exploit the vertical integration technologies in new ASIC and modules concepts for

g, 5th June 20

FE-I4 p

  • SLHC. Split analogue and digital

part using different, individually

  • ptimized technologies:

smaller area (reduce pixel size or

hop, Freiburg

smaller area (reduce pixel size or add more functionality). Place “periphery” used for logic, addressing readout storage

RD50 Worksh

addressing, readout storage, services within active area: 100% fill factor, 4-side buttable

cchiolo, 14th R

Implementation in the CiS production (both n- in-n and n-in-p) of two small pixel matrices to be interfaced with FE-chips using vertical integration

  • technologies. They will be submitted to a multi-
  • A. Mac

17

g y project Tezzaron-Chartered 130 nm CMOS run in the next few months.

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SLIDE 18

Pixel detectors for 3D technologies (II)

009

  • One sensor dedicated to the 3D

version of the FE-I4 test –chip (CPPM, Marseille) where the analog and digital functionality have been divided in two

g, 5th June 20

different tiers:

  • pitch 166.66 μm

hop, Freiburg

  • 48 rows x 7 columns

RD50 Worksh

  • Pixel matrix with 50x50 μm2 pitch to

cchiolo, 14th R

be interfaced to a test chip from LAL:

  • test basic functionality of two-tier chip
  • A. Mac

18

  • charge sharing measurements
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SLIDE 19

Test structures

009

Measurement of the inter-pixel

Readout

Most of the test-structures are common for the n-in-n and n-in-p batches

g, 5th June 20

capacitances:

  • small matrices of 5 x 5 pixels
  • Three pixel sizes (hom and mod p-spray):

Readout pads

hop, Freiburg

  • Three pixel sizes (hom. and mod p-spray):

50 x 400 um² 50 x 100 um²

RD50 Worksh

50 x 50 um2

  • Central pixel and its 1st and 2nd

neighbours are routed out to pads

cchiolo, 14th R

neighbours are routed out to pads

  • r contacted directly
  • Simple single pixel readout
  • A. Mac

Diodes, MOS, MOSFET to measure the process parameters Structures to extract doping profile measurements through SEM analysis

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SLIDE 20

Irradiations and test-beams

009

Irradiations of these devices is foreseen in 2010:

26 M V t i K l h d 24 G V t t CERN t 2 1016

2

g, 5th June 20

  • 26 MeV protons in Karlsruhe and 24 GeV protons at CERN up to 2x1016 n.eq. cm-2
  • reactor neutrons in Ljubliana

FE I3 is radiation resistant only up to 2x1015 n eq /cm2

hop, Freiburg

FE-I3 is radiation-resistant only up to ~ 2x1015 n.eq./cm2..

  • At higher fluences chip-to-chip low-temperature bonding of irradiated sensors to

electronics could be tried

RD50 Worksh

  • Radiation doses that FE-I4 can stand are still to be determined for the final chip.

Test beams for the evaluation of the irradiated devices:

cchiolo, 14th R

Test-beams for the evaluation of the irradiated devices:

  • July 2010 for structures bonded to FE-I3
  • 2011 for structures bonded to FE-I4
  • A. Mac

20

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SLIDE 21

Summary

009

Suitability of planar pixel sensors for the highest fluences and larger area is being investigated

g, 5th June 20

being investigated Choice of bulk material driven by the RD50 results on p-type Fz silicon and n-

hop, Freiburg

Choice of bulk material driven by the RD50 results on p type Fz silicon and n and p-type MCz silicon.

RD50 Worksh

Wafer layouts completed and submitted to CiS for the n-in-n and n-in-p batches

cchiolo, 14th R

First results from irradiations and test-beams foreseen in 2010

  • A. Mac
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SLIDE 22

009 g, 5th June 20

Back up slides

hop, Freiburg

Back-up slides

RD50 Worksh cchiolo, 14th R

  • A. Mac

22

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SLIDE 23

P-type pixel modules

009

Production on p-type material need to isolate the FE chip from the HV present at the sensor edges on the front side

  • A BCB layer as additional passivation on the sensor front side should

g, 5th June 20

provide the necessary isolation on the surface. Isolation capability tested up to 1000 V. Need R&D to isolate also the lateral sides (see PSI tests in J.A. Sibille talk, this workshop).

hop, Freiburg RD50 Worksh cchiolo, 14th R

IZM can deposit BCB as a post-processing step on 4” wafers before

  • A. Mac

23 the UBM step additional mask needed Post-processing on full wafers