Beam test results of an SOI monolithic pixel sensor SOFIST for the - PowerPoint PPT Presentation

Shun Ono (KEK) , Miho Yamada and SOI Pixel R&D group 1 The 9th International Workshop on Semiconductor Pixel Detectors for Particles and Imaging (PIXEL2018) Academia Sinica, Taipei December 11th, 2018 Beam test results of an SOI monolithic pixel sensor SOFIST for the ILC vertex detector

2 SOI Pixel Detector • Monolithic pixel detector based on Silicon-On-Insulator • 0.2 μ m FD-SOI CMOS process by Lapis Semiconductor Co. Ltd. • SOI Pixel sensor features • Monolithic structure: (No bumps) • Small, highly integrated pixel circuit • Low material budget • CMOS circuit fabricated on buried oxide layer (BOX) • Low capacitance: High speed, Low power circuit • High resistivity substrate • Fully depleted sensor • Double SOI structure: Additional silicon layer in the BOX • Crosstalk reduction between circuit and sensor layers. • High radiation tolerance (~1MGy): compensation of trapped holes in the BOX

3 International Linear Collider: Detector system • ILC experiment: e+,e- linear collider • Precise measurement of Higgs boson, Search for BSM physics • Need vertex detector with high accuracy spatial resolution for reconstructing the physics events • Development of new pixel detector optimized for ILC experiment • Realizing fine pixel detector with SOI technology

4 Vertex detector requirement • Positon resolution: < 3 um ILC beam structure • Material thickness ： < 100 um Si thickness 200 ms (5 Hz) bunch train • Reducing multiple scattering • Low power (for reducing cooling system): 50 mW/cm 2 1312 bunches • Time resolution : ~ 554 ns bunch interval • Beam bunch identification • Detector occupancy (hit rate) : 1312 bunches in one train 554 ns • Multiple hits in one pixel • Data transfer : 200 ms beam train interval • Radiation Hardness : • TID: 1 kGy/year • NIEL: 1011 1MeV neq/cm2/year

5 Specifications of new SOI detector • Specification of new SOI sensor optimized for ILC vertex detector • Positon resolution: < 3 um • Pixel size: 20 × 20 um 2 • Calculate weighted center of charges → Recording charge signal in each pixel • Time resolution: ~554 ns (Beam bunch interval) • Identify collision bunches of hit events → Recording hit timestamp • Multiple hits in one pixel • Store hit informations during one beam train → Implementing multiple memories • Data transfer: 200 ms • High speed data processing → On-chip ADC, Digital circuits for data sparsificaion Design high-functional SOI sensor with measuring both hit-position and time.

6 SOFIST: Pixel design • SOFIST: SOI sensor for Fine measurement space and time • SOFIST Pixel function Timestamp memory SW1 Timestamp • Pre-amplifier: CSA output Ramp signal SW2 • Comparator: Hit-signal discrimination • Shift register: Memory sequencer SW1 SW2 D Q D Q Vth • Multiple Analog-signal memories Shift-register Comparator SW1 • Record signal amplitude Signal output Pre-amp SW2 • Multiple Timestamp memories • Record hit timing by holding ramp voltage Analog signal memory

7 SOFIST: chip design SOFIST Ver.1 Ver.2 Ver.3 Ver.4 (3D) Full functionality Hit detection Full functionality Pixel circuit Analog signal 3D stacking Timestamp 4.45 × 4.45 6.0 × 6.0 4.45 × 4.45 2.9 × 2.9 Chip size (mm) Pixel size ( μ m) 20 × 20 25 × 25 30 × 30 20 × 20 Functions Pre-amplifier Pre-amplifier Pre-amplifier Analog signal memory Comparator Comparator Shift-register Shift-register Analog signal memory (2hits) Analog signal memory (3hits) or Timestamp memory (3hits) Timestamp memory (2hits)

8 SOFIST Ver.1 • Pixel circuit • Pixel size: 20 × 20 μ m 2 Timestamp memory SW1 Timestamp • Pre-amplifier: Gain = 32 μ V/e- output Ramp signal SW2 • Analog signal memories: 2 Hits • On-chip: 8 bit column-parallel ADC Ver.1 pixel SW1 SW2 D Q D Q • Sensor layer: 500 μ m thickness Vth Pixel layout Shift-register Comparator SW1 Signal output Pre-amp SW2 Analog signal memory

9 SOFIST Ver.1: Test result • Beam test @ Fermilab Test beam Facility (Jan. 2017) Readout, Sensor depletion 12 bit ADC, 500 μ m (Full-depletion) • • Proton beam: 120 GeV 12 bit ADC, 200 μ m • 8 bit ADC (On-chip), 500 μ m • • Sensor bias: 130 V, 15 V (Depletion = 500, 200 μ m) • Readout: external ADC (12 bit), on-chip ADC (8 bit) • Signal-to-noise • Position resolution • Summing 5 x 5 pixels around hit • Calculate weighted center of charges (5 × 5 pixels). • Pixel noise: ~1.4 ADU (External ADC (12 bit)) • Difference between SOFIST hit and reconstructed track Signal spectrum Residual distribution Residual X: 5 h_resx_5 h_resx_5 Events 2401 2401 Entries Entries 220 0.1677 0.1677 Mean Mean Std Dev Std Dev 2.721 2.721 200 2 2 / ndf / ndf χ χ χ χ 12.58 / 9 12.58 / 9 180 227.7 227.7 ± ± 7.6 7.6 Constant Constant 0.1668 0.1668 0.0386 0.0386 Mean Mean ± ± 160 Sigma Sigma 1.367 1.367 0.035 0.035 ± ± 140 Sigma = 1.37 μ m S/N ~ 300 120 100 = 1.33 μ m ~ 124 80 = 1.49 μ m 60 40 20 0 15 10 5 0 5 10 15 − − − − − − Residual X [um]

10 SOFIST Ver.2 • Pixel circuit Timestamp memory SW1 Timestamp output Ramp signal • Pixel size: 25 × 25 μ m 2 SW2 Ver.2 pixel (Analog signal) • In-pixel comparator and 2-stage shift-register SW1 SW2 D Q D Q Vth • Analog signal or Timestamp memories: 2 Hits Shift-register Comparator SW1 Signal output • Sensor layer: Thinned to 65 μ m Pre-amp SW2 Pixel layout Analog signal memory Timestamp memory SW1 Timestamp output Ramp signal SW2 Ver.2 pixel (Timestamp) SW1 SW2 D Q D Q Vth Shift-register Comparator SW1 Signal output Pre-amp SW2 Analog signal memory

11 SOFIST Ver.2: Pixel operation • Analog signal pixel: Pixel response by test pulse input • Operation of in-pixel comparator and Shift-register (memory sequencer) 1st memory and shift-register 2nd memory and shift-register 1st shift register 2nd shift register Pixel reset Pixel reset 1st memory 2nd memory Test pulse Test pulse 1st signal input 2nd signal input 1st signal input 2nd signal input • Latching hit-signal amplitude by comparator • Storing two hit signals in two memories by shift-register

12 SOFIST Ver.2: Pixel operation • Timestamp pixel: Pixel response by test pulse input Timestamp responce Timestamp [ADU] 2500 Timestamp [ADU] • Calibration of analog timestamp 2000 1500 Timestamp pixel output 1000 500 Ramp signal 0 0 100 200 300 400 500 600 Test-pulse input [ µ s] Test pulse [ μ s] Timestamp memory Timestamp fluctuation (One pixel) Timestamp signal h1_sig_17_20 h1_sig_17_20 Entry Entries Entries 2000 2000 Mean Mean 249.6 249.6 400 RMS RMS 0.9257 0.9257 Test pulse 2 2 χ χ / ndf / ndf 27.03 / 9 27.03 / 9 350 Constant Constant 433.1 433.1 ± ± 11.4 11.4 Mean Mean 249.5 249.5 0.0 0.0 ± ± 300 Sigma Sigma 0.9094 0.9094 ± ± 0.0124 0.0124 Signal input 250 Sigma ~ 1 μ s 200 150 100 50 0 240 242 244 246 248 250 252 254 256 258 260 Timestamp [ s] µ Test pulse [ μ s]

13 SOFIST Ver.2: Test result • Beam test @ Fermilab Test beam Facility (Feb. 2018) • Proton beam: 120 GeV Ver.2 chip Readout board • The data analysis is still underway. SOFIST Ver.2 Pixel size: 25 × 25 μ m 2 Active area: 2.0 × 1.6 mm 2 30 mm SOFIST Ver.2 MPPC (Trigger detector) Beam Proton beam INTPIX INTPIX4 (SOIPIX): Tracker Pixel size: 17 × 17 μ m 2 Active area: 14.1 × 8.7 mm 2

14 Beam test result Hit detection and time-stamping results of proton beams • Beam test setup 30 mm SOFIST Ver.2 MPPC (Trigger detector) Timestamp di ff erence Beam Sigma = 2.19 μ s Intrinsic resolution: Sigma/ √ 2 ~ 1.55 μ s INTPIX Event display Different pixel color → Different hit timing

15 SOFIST Ver.3 • Pixel circuit • Pixel size: 30 × 30 μ m 2 Timestamp memory SW1 • In-pixel comparator and 2-stage shift-register Timestamp output Ramp signal • Analog signal and Timestamp memories: 3 Hits SW2 • Sensor layer: Thinned to 65 μ m SW1 SW2 D Q D Q Vth Shift-register Comparator SW1 Signal output Pre-amp SW2 Analog signal memory

16 Ver.3 test result • Pixel response by β -ray (Sr-90) • Analog signal memory: charge deposition in each pixel • Timestamp memory: detection timing of each β -ray track Analog signal map Timestamp map Next beam test is planned at February, 2019

17 Test results and issues • Position resolution: < 3 μ m • SOFIST Ver.1 achieved 1.33 μ m resolution. • Pixel size: 20 × 20 μ m 2 , Sensor thickness: 200 μ m • Time resolution: ~554 ns • SOFIST Ver.2 timestamp has 1.55 μ s resolution (Preliminary). → More precise memory and low noise circuits. • Low material budget: < 100 μ m sensor and low power circuit. • Hit signal can be detected with 65 μ m sensor. The position resolution with 65 μ m is under analyzing. • Pixel circuit has high power consumption (~500 mW/cm 2 ). → Design/Operate lower power pixel. • Detector occupancy (hit rate): Multiple pixel memories • Ver.3 pixel has 3 analog and timestamp memories. The pixel size became 30 μ m pitch. → Small and high-integrated pixel by 3D stacking technology.