Beam test results of an SOI monolithic pixel sensor SOFIST for the - - PowerPoint PPT Presentation

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Beam test results of an SOI monolithic pixel sensor SOFIST for the - - PowerPoint PPT Presentation

May 11, 2023 48 likes •284 views

Shun Ono (KEK) , Miho Yamada and SOI Pixel R&D group 1 The 9th International Workshop on Semiconductor Pixel Detectors for Particles and Imaging (PIXEL2018) Academia Sinica, Taipei December 11th, 2018 Beam test results of an SOI

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SLIDE 1

Beam test results of an SOI monolithic pixel sensor SOFIST for the ILC vertex detector

Shun Ono (KEK), Miho Yamada and SOI Pixel R&D group

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The 9th International Workshop on Semiconductor Pixel Detectors for Particles and Imaging (PIXEL2018) Academia Sinica, Taipei December 11th, 2018

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SLIDE 2

SOI Pixel Detector

  • Monolithic pixel detector based on Silicon-On-Insulator
  • 0.2 μm FD-SOI CMOS process by Lapis Semiconductor Co. Ltd.
  • SOI Pixel sensor features
  • Monolithic structure: (No bumps)
  • Small, highly integrated pixel circuit
  • Low material budget
  • CMOS circuit fabricated on buried oxide layer (BOX)
  • Low capacitance: High speed, Low power circuit
  • High resistivity substrate
  • Fully depleted sensor
  • Double SOI structure: Additional silicon layer in the BOX
  • Crosstalk reduction between circuit and sensor layers.
  • High radiation tolerance (~1MGy): compensation of trapped holes in the BOX

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SLIDE 3

International Linear Collider: Detector system

  • ILC experiment: e+,e- linear collider
  • Precise measurement of Higgs boson, Search for BSM physics
  • Need vertex detector with high accuracy spatial resolution for reconstructing the physics events
  • Development of new pixel detector optimized for ILC experiment
  • Realizing fine pixel detector with SOI technology

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SLIDE 4

Vertex detector requirement

  • Positon resolution: < 3 um
  • Material thickness： < 100 um Si thickness
  • Reducing multiple scattering
  • Low power (for reducing cooling system): 50 mW/cm2
  • Time resolution: ~ 554 ns bunch interval
  • Beam bunch identification
  • Detector occupancy (hit rate): 1312 bunches in one train
  • Multiple hits in one pixel
  • Data transfer: 200 ms beam train interval
  • Radiation Hardness:
  • TID: 1 kGy/year
  • NIEL: 1011 1MeV neq/cm2/year

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ILC beam structure

200 ms (5 Hz) bunch train 554 ns 1312 bunches

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SLIDE 5

Specifications of new SOI detector

  • Specification of new SOI sensor optimized for ILC vertex detector
  • Positon resolution: < 3 um
  • Pixel size: 20 × 20 um2
  • Calculate weighted center of charges → Recording charge signal in each pixel
  • Time resolution: ~554 ns (Beam bunch interval)
  • Identify collision bunches of hit events → Recording hit timestamp
  • Multiple hits in one pixel
  • Store hit informations during one beam train → Implementing multiple memories
  • Data transfer: 200 ms
  • High speed data processing → On-chip ADC, Digital circuits for data sparsificaion

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Design high-functional SOI sensor with measuring both hit-position and time.

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SLIDE 6

SOFIST: Pixel design

  • SOFIST: SOI sensor for Fine measurement space and time
  • SOFIST Pixel function
  • Pre-amplifier: CSA
  • Comparator: Hit-signal discrimination
  • Shift register: Memory sequencer
  • Multiple Analog-signal memories
  • Record signal amplitude
  • Multiple Timestamp memories
  • Record hit timing by holding ramp voltage

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D Q D Q

SW1 SW2 SW1 SW2 Pre-amp Comparator Vth SW1 SW2 Analog signal memory Timestamp memory Shift-register Ramp signal Timestamp

  • utput

Signal output

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SLIDE 7

SOFIST: chip design

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Ver.1 Ver.2 Ver.3 Ver.4 (3D) SOFIST

Functions Chip size (mm)

2.9 × 2.9 4.45 × 4.45 6.0 × 6.0 4.45 × 4.45

Pixel size (μm)

20 × 20 25 × 25 30 × 30 20 × 20 Pre-amplifier Analog signal memory Pre-amplifier Comparator Shift-register Analog signal memory (2hits)

  • r

Timestamp memory (2hits) Pre-amplifier Comparator Shift-register Analog signal memory (3hits) Timestamp memory (3hits) Analog signal Hit detection Timestamp Full functionality Full functionality 3D stacking

Pixel circuit

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SLIDE 8

D Q D Q

SW1 SW2 SW1 SW2 Pre-amp Comparator Vth SW1 SW2 Analog signal memory Timestamp memory Shift-register Ramp signal Timestamp

  • utput

Signal output

SOFIST Ver.1

  • Pixel circuit
  • Pixel size: 20 × 20 μm2
  • Pre-amplifier: Gain = 32 μV/e-
  • Analog signal memories: 2 Hits
  • On-chip: 8 bit column-parallel ADC
  • Sensor layer: 500 μm thickness

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Pixel layout

Ver.1 pixel

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SLIDE 9

SOFIST Ver.1: Test result

  • Beam test @ Fermilab Test beam Facility (Jan. 2017)
  • Proton beam: 120 GeV
  • Sensor bias: 130 V, 15 V (Depletion = 500, 200 μm)
  • Readout: external ADC (12 bit), on-chip ADC (8 bit)

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χ

− − −

χ

h_resx_5

Entries 2401 Mean 0.1677 Std Dev 2.721 / ndf

2

χ 12.58 / 9 Constant 7.6 ± 227.7 Mean 0.0386 ± 0.1668 Sigma 0.035 ± 1.367

Residual X [um] 15 − 10 − 5 − 5 10 15 Events 20 40 60 80 100 120 140 160 180 200 220

h_resx_5

Entries 2401 Mean 0.1677 Std Dev 2.721 / ndf

2

χ 12.58 / 9 Constant 7.6 ± 227.7 Mean 0.0386 ± 0.1668 Sigma 0.035 ± 1.367

Residual X: 5

Signal spectrum Residual distribution

  • Signal-to-noise
  • Summing 5 x 5 pixels around hit
  • Pixel noise: ~1.4 ADU (External ADC (12 bit))

S/N ~ 300 ~ 124

  • Position resolution
  • Calculate weighted center of charges (5 × 5 pixels).
  • Difference between SOFIST hit and reconstructed track

Sigma = 1.37 μm = 1.33 μm = 1.49 μm

Readout, Sensor depletion

  • 12 bit ADC, 500 μm (Full-depletion)
  • 12 bit ADC, 200 μm
  • 8 bit ADC (On-chip), 500 μm
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SLIDE 10

SOFIST Ver.2

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D Q D Q

SW1 SW2 SW1 SW2 Pre-amp Comparator Vth SW1 SW2 Analog signal memory Timestamp memory Shift-register Ramp signal Timestamp

  • utput

Signal output

D Q D Q

SW1 SW2 SW1 SW2 Pre-amp Comparator Vth SW1 SW2 Analog signal memory Timestamp memory Shift-register Ramp signal Timestamp

  • utput

Signal output

  • Pixel circuit
  • Pixel size: 25 × 25 μm2
  • In-pixel comparator and 2-stage shift-register
  • Analog signal or Timestamp memories: 2 Hits
  • Sensor layer: Thinned to 65 μm

Pixel layout Ver.2 pixel (Analog signal) Ver.2 pixel (Timestamp)

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SLIDE 11

SOFIST Ver.2: Pixel operation

  • Analog signal pixel: Pixel response by test pulse input
  • Operation of in-pixel comparator and Shift-register (memory sequencer)

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1st memory and shift-register 2nd memory and shift-register

1st shift register Pixel reset 1st memory Test pulse

1st signal input 2nd signal input

2nd shift register Pixel reset 2nd memory Test pulse

1st signal input 2nd signal input

  • Latching hit-signal amplitude by comparator
  • Storing two hit signals in two memories by shift-register
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SLIDE 12

SOFIST Ver.2: Pixel operation

  • Timestamp pixel: Pixel response by test pulse input
  • Calibration of analog timestamp

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s] µ Test-pulse input [ 100 200 300 400 500 600 Timestamp [ADU] 500 1000 1500 2000 2500

h1_sig_17_20

Entries 2000 Mean 249.6 RMS 0.9257 / ndf

2

χ 27.03 / 9 Constant 11.4 ± 433.1 Mean 0.0 ± 249.5 Sigma 0.0124 ± 0.9094

s] µ Timestamp [ 240 242 244 246 248 250 252 254 256 258 260 Entry 50 100 150 200 250 300 350 400

h1_sig_17_20

Entries 2000 Mean 249.6 RMS 0.9257 / ndf

2

χ 27.03 / 9 Constant 11.4 ± 433.1 Mean 0.0 ± 249.5 Sigma 0.0124 ± 0.9094

Timestamp signal

Ramp signal Timestamp memory Test pulse

Signal input

Timestamp pixel output

Timestamp responce Test pulse [μs] Timestamp [ADU] Timestamp fluctuation (One pixel) Test pulse [μs] Sigma ~ 1 μs

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SLIDE 13

SOFIST Ver.2: Test result

  • Beam test @ Fermilab Test beam Facility (Feb. 2018)
  • Proton beam: 120 GeV
  • The data analysis is still underway.

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SOFIST Ver.2 INTPIX MPPC (Trigger detector) Beam 30 mm

SOFIST Ver.2 Pixel size: 25 × 25 μm2 Active area: 2.0 × 1.6 mm2 INTPIX4 (SOIPIX): Tracker Pixel size: 17 × 17 μm2 Active area: 14.1 × 8.7 mm2

Proton beam Ver.2 chip Readout board

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SLIDE 14

Beam test result

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SOFIST Ver.2 INTPIX MPPC (Trigger detector) Beam 30 mm

Beam test setup Event display Different pixel color → Different hit timing Timestamp difference

Sigma = 2.19 μs Intrinsic resolution: Sigma/√2 ~ 1.55 μs

  • Hit detection and time-stamping results of proton beams
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SLIDE 15

SOFIST Ver.3

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D Q D Q

SW1 SW2 SW1 SW2 Pre-amp Comparator Vth SW1 SW2 Analog signal memory Timestamp memory Shift-register Ramp signal Timestamp

  • utput

Signal output

  • Pixel circuit
  • Pixel size: 30 × 30 μm2
  • In-pixel comparator and 2-stage shift-register
  • Analog signal and Timestamp memories: 3 Hits
  • Sensor layer: Thinned to 65 μm
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SLIDE 16

Ver.3 test result

  • Pixel response by β-ray (Sr-90)
  • Analog signal memory: charge deposition in each pixel
  • Timestamp memory: detection timing of each β-ray track

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Analog signal map Timestamp map Next beam test is planned at February, 2019

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SLIDE 17

Test results and issues

  • Position resolution: < 3 μm
  • SOFIST Ver.1 achieved 1.33 μm resolution.
  • Pixel size: 20 × 20 μm2, Sensor thickness: 200 μm
  • Time resolution: ~554 ns
  • SOFIST Ver.2 timestamp has 1.55 μs resolution (Preliminary).

→ More precise memory and low noise circuits.

  • Low material budget: < 100 μm sensor and low power circuit.
  • Hit signal can be detected with 65 μm sensor. The position resolution with 65 μm is under analyzing.
  • Pixel circuit has high power consumption (~500 mW/cm2).

→ Design/Operate lower power pixel.

  • Detector occupancy (hit rate): Multiple pixel memories
  • Ver.3 pixel has 3 analog and timestamp memories. The pixel size became 30 μm pitch.

→ Small and high-integrated pixel by 3D stacking technology.

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SLIDE 18

3D stacking technology

  • SOI pixel detector with 3D stacking technology
  • Connect the upper and lower chip by micro-bump: Tohoku MicroTec Co., Ltd.
  • Pixel size reduction: 30 × 30 μm2 → 20 × 20 μm2

18 Up Upper Ch r Chip ip Lo Lower C Chi hip An Anal alog FE + Senso sor

Lower pixel

  • Pre-amp
  • Comparator

Upper pixel (Inverted)

  • Shift-register
  • Analog memory x3
  • Timestamp x3

Bump pad

3D-SOI chip: cross-section Au Micro-bump (Cylinder bump) Ver.4: Pixel layout

20 μm

3.5 μm

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SLIDE 19

3D-stacking technology

  • Bump production on SOFIST Ver.4
  • SOFIST Ver.4 will be shipped in 2018.

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Pixel array Pixel

20 um

Dummy bump Bump pad 20 μm

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SLIDE 20

Summary

  • SOI pixel detector SOFIST is designed for ILC vertex detector.
  • Design high-functional SOI sensor with measuring both hit-position and time.
  • SOFIST has been tested in FermiLab beam
  • SOFIST Ver.1: 20 μm pixel, Depletion layer: 200 μm
  • Position resolution: 1.33 μm
  • SOFIST Ver.2: 25 μm pixel, Depletion layer: 65 μm
  • Time resolution: ~1.55 μs
  • SOFIST Ver.3: 30μm pixel with full-functionality
  • To be tested at FermiLab
  • SOFIST Ver.4: 20μm pixel, 3D stacked sensor
  • Fabrication is underway. Stacked chip will be shipped in 2018.

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SLIDE 21

Backup

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SLIDE 22

3D stacking: Micro bump

  • 3D integration of SOI sensor chip
  • Micro-bumps are developed by photolithography process
  • Bump size: 3.5umφ, Minimum pitch: 7μm
  • Connection yield: > 99.5 %

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  • Micro-bump

Bump formation (Au spattering) Cross sectional view after stacking

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SLIDE 23

3D stacking: stack process

  • 1. Bump formation

(Micro bumps are formed

  • n both chips.)
  • 2. Stacking and pressing 2 chips

Inducing glue between chips

  • 3. Removing upper substrate

Forming IO pads.

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