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InGaSb p-Channel Self-Aligned FinFETs with 10 nm Fin-Width Using - - PowerPoint PPT Presentation

InGaSb p-Channel Self-Aligned FinFETs with 10 nm Fin-Width Using Sb-Compatible Digital Etch W. Lu 1 , I. P. Roh 2 , D.-M. Geum 2 , S.-H. Kim 2 , J. D. Song 2 , L. Kong 1 , and J. A. del Alamo 1 1 Microsystems Technology Laboratories, MIT


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SLIDE 1

InGaSb p-Channel Self-Aligned FinFETs with 10 nm Fin-Width Using Sb-Compatible Digital Etch

  • W. Lu1, I. P. Roh2, D.-M. Geum2, S.-H. Kim2, J. D. Song2, L. Kong1,

and J. A. del Alamo1

1Microsystems Technology Laboratories, MIT 2Korea Institute of Science and Technology

December 5, 2017 Sponsors:

DTRA KIST Lam Research SRC

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SLIDE 2

Outline

  • Motivation
  • Key technology: III-Sb-compatible digital etch
  • InGaSb p-channel FinFET fabrication
  • Electrical characteristics
  • Conclusions

2

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SLIDE 3

3

Properties of III-Sb:

  • High µn
  • High µp
  • Strong strain effect
  • Eg engineering
  • Applications in

photonics, etc.

InSb GaSb

[Miki, 1975] [Kawashima and Kataoka, JJAP 1979] [del Alamo, Nature, 2011]

Electron mobility Hole mobility in QW-FETs

A Case for III-Sb

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SLIDE 4

4

III-Sb Transistor Research

InGaAs (IEEE)

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SLIDE 5

5

III-Sb Transistor Research

Gu, IEDM 2011 Vardi, EDL 2016 Zhou, VLSI 2016 Waldron, VLSI 2016 Vardi, IEDM 2015 Zota, IEDM 2016 Zhao, IEDM 2013

InGaAs (IEEE)

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SLIDE 6

6

III-Sb Transistor Research

III-Sb transistors (All publications) InGaAs (IEEE)

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SLIDE 7

7

III-Sb Transistor Research

InSb QW p-FET Radosavljevic, IEDM ’08 InGaSb p-MOSFET Nainani, IEDM ’10 InGaSb p-SOI Nishi, VLSI ’15 InGaSb p-FinFET Lu, IEDM ’15 InAs/GaSb TFET Memišević, EDL ’16 InAs/AlSb/GaSb HEMT

  • B. Bennett, JVST ’00

InAs/GaSb CMOS Goh, IEDM ’15

III-Sb transistors (All publications) InGaAs (IEEE)

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SLIDE 8

8

Digital etch: key of sub-10 nm InGaAs transistors

Challenges: III-Sb Digital Etch

D = 8 nm WF = 5 nm D = 5 nm

[Vardi, IEDM 2017] [Lu, EDL, 2017]

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SLIDE 9

9

  • Wf limited by EBL and RIE

Challenges: III-Sb Digital Etch

XSEM of InGaSb FinFET

[Lu, IEDM, 2015]

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SLIDE 10

10

XSEM of InGaSb FinFET Wf = 30 nm, Lg = 100 nm

  • Wf limited by EBL and RIE
  • Suffers from large off current

Challenges: III-Sb Digital Etch

  • 0.8
  • 0.4

0.0 100 200 300

ID (µA/µm) VDS (V)

VGS = 0.5 V to -3.5 V

[Lu, IEDM, 2015]

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SLIDE 11

11

GaSb MOSCAPs

  • Previous research: HCl cleans GaSb surface

HCl Digital Etch on III-Sb

As-Is HCl

[Nainani, JAP 2011]

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SLIDE 12

12

HCl Digital Etch on III-Sb

  • 3
  • 2
  • 1

1 1x10

1

1x10

2

1x10

3

after HCl

ID (µA/µm) VGS (V)

Vds= -1.05 V

[Lu, IEDM, 2015]

FinFETs: only mild improvement of off current

[Nainani, JAP 2011]

GaSb MOSCAPs

  • Previous research: HCl cleans GaSb surface

As-Is HCl

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SLIDE 13

13

1% HCl 30s After RIE

  • HCl etches the InGaSb sidewall

Issue with HCl Digital Etch

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SLIDE 14

14

1% HCl 30s After RIE

  • HCl etches the InGaSb sidewall

Issue with HCl Digital Etch

DI water 2 min

Water-based HCl problematic for III-Sb DE

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SLIDE 15

15

  • Self-limiting process
  • No damage on the sidewall

20 nm

10% HCl:IPA 2 min After RIE

Alcohol-based Digital Etch

20 nm

[Lu, EDL, 2017]

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SLIDE 16

16

D = 20 nm D = 20 nm

Alcohol-based Digital Etch

2 4 6 20 40 60

VNW Radius (nm) Digital Etch Cycles

First digital etch on III-Sb: HCl:IPA + O2 plasma 10 nm

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SLIDE 17

17

Etch rate ↓ after multiple DE cycles

D = 20 nm D = 20 nm

Alcohol-based Digital Etch

2 4 6 20 40 60 0.6 nm/cycle

VNW Radius (nm) Digital Etch Cycles

2 nm/cycle

First digital etch on III-Sb: HCl:IPA + O2 plasma

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SLIDE 18

18

  • r (III-Sb) ↓ after 3 cycles
  • r (III-As) >> r (III-Sb)

InGaSb InAs HSQ 25 nm No DE 10 cycles r = 0.2 nm/cycle 16 nm 19 nm 3 cycles r = 1 nm/cycle

Alcohol-based Digital Etch

AlGaSb

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SLIDE 19

Oxidation of GaSb:

  • In air:

‒Ga2O3, Sb2O3

19

Sb-compatible Digital Etch

[Liu, JVST B. 2002]

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SLIDE 20

Oxidation of GaSb:

  • In air:

‒Ga2O3, Sb2O3

  • In strong oxidation agents:

‒Ga2O3, Sb2O3, Sb2O5 (insoluble in aqueous acid/alkali)

20

DE = oxidation + dissolution, both critical for III-Sb!

III-Sb-compatible Digital Etch

[Liu, JVST B. 2002]

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SLIDE 21

Survey of digital etch combinations:

21

Best results: RT O2 atmosphere + HCl:IPA

III-Sb-compatible Digital Etch

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SLIDE 22

O2 oxidation + HCl:IPA, IPA rinsing

22

r (III-As) = r (III-Sb)

25 nm No DE 9 nm 4 cycles r = 2 nm/cycle 17 nm 2 cycles r = 2 nm/cycle

III-Sb-compatible Digital Etch

InGaSb InAs HSQ AlGaSb

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SLIDE 23

23

  • Channel μp = 1175 cm2/V∙s
  • Buffer/channel resistivity ~ 109

InGaSb FinFETs

Heterostructure (MBE at KIST) Composite cap

  • 1.1% strain

Hc = 23 nm Graded buffer TEM

20 nm

23 nm InGaSb 6 nm InAlSb p+ cap AlGaSb

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SLIDE 24

24

  • Ni Ohmic contact
  • SiO2 spacer
  • Gate recess (dry + wet)
  • Fin RIE
  • Digital etch
  • Al2O3/Al Gate stack
  • Via + metal

InGaSb FinFET Process

HSQ InGaSb Al2O3/Al

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SLIDE 25

25

Rc = 22 Ω∙μm  4x reduction of Rc from 2015 FinFETs

Ohmic Contacts

Ni contacts, 350 °C RTA, 3 min

100 200 300 400 10

1

10

2

10

3

10

4

Ni W

Rc (Ω⋅µm) RTA Temp (°C)

Mo

Ni [MIT '15]

[Guo, EDL, 2015]

5 10 15 20 1 2 3 4 Na = 1⋅10

19 cm

  • 3

Rc = 93 Ω⋅µm

RTotal⋅W (Ω⋅µm) Ld (µm)

Na = 3⋅10

19 cm

  • 3

Rc = 22 Ω⋅µm ×10

4

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SLIDE 26

26

High-quality simultaneous InAs and GaSb etching

Fin Etch

BCl3/Ar/SiCl4 3:11:0.4, 250°C This work BCl3/N2 13.5:5.5, 250°C [Lu, IEDM 2015]

50 nm InAs GaSb

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SLIDE 27

Finished devices

27

  • 3.5 nm Al2O3 gate dielectric
  • Final FGA anneal at 150 °C for 3 min

InGaSb FinFET Process

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SLIDE 28

28

  • Narrowest Wf = 10 nm
  • Fin AR = 2.3

InGaSb FinFET Process

50 nm 84° HSQ InGaSb Al2O3 AlGaSb 10 nm 10 nm 3.5 nm 23 nm

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SLIDE 29

29

  • S ~ 260 mV/dec
  • gm,max= 160 μS/μm
  • Single fin device: current fluctuations

Electrical Characteristics

  • 1.0
  • 0.8
  • 0.6
  • 0.4
  • 0.2

0.0 50 100 150 200

ID (µA/µm) VDS (V)

VGS = -1 V to 1 V in 0.4 V step

  • 0.5

0.0 0.5 10

  • 1

10 10

1

10

2

VDS = -0.5 V VDS = -50 mV

ID (µA/µm) VGS (V)

Smin = 260 mV/dec

  • 1.0
  • 0.5

0.0 0.5 1.0 50 100 150 200 VDS = -50 mV VDS = -0.5 V

gm (µS/µm) VGS (V)

Wf = 10 nm, Lg = 20 nm, Nf = 1

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SLIDE 30

30

Electrical Characteristics

  • 1.0
  • 0.8
  • 0.6
  • 0.4
  • 0.2

0.0 1 2 3 4

ID (µA/µm) VDS (V)

VGS = -1 V to 1 V in 0.4 V step

  • 0.5

0.0 0.5 10

  • 3

10

  • 2

10

  • 1

10 VDS = -0.5 V VDS = -50 mV

ID (µA/µm) VGS (V)

Smin = 290 mV/dec

Wf = 10 nm, Lg = 1 μm, Nf = 100

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SLIDE 31

31

Electrical Characteristics

  • 1.0
  • 0.8
  • 0.6
  • 0.4
  • 0.2

0.0 1 2 3 4

ID (µA/µm) VDS (V)

VGS = -1 V to 1 V in 0.4 V step

Wf = 10 nm, Lg = 1 μm, Nf = 100 Significant improvement over 1st gen FinFETs

  • 1.0
  • 0.8
  • 0.6
  • 0.4
  • 0.2

0.0 4 8 12

ID (µA/µm) VDS (V)

Wf = 30 nm, Lg = 1 μm

[Lu, IEDM, 2015]

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SLIDE 32

32

Lg ↓  gm↑ Wf ↓  gm ↓

gm Scaling

100 1000 100 200 300

Wf = 26 nm Wf = 18 nm Wf = 14 nm Wf = 10 nm

gm (µS/µm) Lg (nm) Wf ↓

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SLIDE 33

33

ON Resistance

20 40 60 80 100 120 2 4 6 8 10

RSD

Ron (kΩ⋅µm) Lg (nm)

Wf = 26 → 10 nm Rf

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SLIDE 34

34

ON Resistance

10 100 1 10 100

Rf (kΩ/฀) Wf (nm)

  • 1

20 40 60 80 100 120 2 4 6 8 10

RSD

Ron (kΩ⋅µm) Lg (nm)

Wf = 26 → 10 nm Rf

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SLIDE 35

35

Rf and RSD ~ 1/Wf

ON Resistance

10 100 1 10 100

Rf (kΩ/฀) Wf (nm)

  • 1

10 100 0.1 1 10

  • 1

RSD (kΩ⋅µm) Wf (nm)

20 40 60 80 100 120 2 4 6 8 10

RSD

Ron (kΩ⋅µm) Lg (nm)

Wf = 26 → 10 nm Rf

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SLIDE 36

36

Wf ↓  better VT roll-up

VT Scaling

10 100 1000 0.0 0.4 0.8 1.2

Wf = 26 nm Wf = 18 nm Wf = 14 nm Wf = 10 nm

VT (V) Lg (nm)

Wf ↓

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SLIDE 37

37

1 DE cycle significantly improves off current

Off-state Current

Wf = 20 nm, Lg = 1 µm

  • 1.0
  • 0.5

0.0 0.5 1.0 10

  • 2

10

  • 1

10 10

1

10

2

1 DE cycle

ID (µA/µm) VGS (V)

0 DE cycle

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SLIDE 38

38

Off-state Current

  • 1.0
  • 0.5

0.0 0.5 1.0 10

  • 2

10

  • 1

10 10

1

10

2

4 DE cycle 1 DE cycle

ID (µA/µm) VGS (V)

0 DE cycle

Wf = 20 nm, Lg = 1 µm

Device degrades after multiple DE cycles

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SLIDE 39

39

  • Buffer is damaged after multiple DE cycles

Off-state Current

  • 1.0
  • 0.5

0.0 0.5 1.0 10

  • 2

10

  • 1

10 10

1

10

2

4 DE cycle 1 DE cycle

ID (µA/µm) VGS (V)

0 DE cycle

3 cycles of DE InGaSb AlGaSb

Wf = 20 nm, Lg = 1 µm

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SLIDE 40

40

  • Buffer is damaged after multiple DE cycles
  • AlGaSb is very reactive

Exposure in air after fin etch

Off-state Current

  • 1.0
  • 0.5

0.0 0.5 1.0 10

  • 2

10

  • 1

10 10

1

10

2

4 DE cycle 1 DE cycle

ID (µA/µm) VGS (V)

0 DE cycle

3 cycles of DE InGaSb AlGaSb

Wf = 20 nm, Lg = 1 µm

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SLIDE 41

41

  • 0.6
  • 0.4
  • 0.2

0.0 0.2 0.4 0.6 10

  • 3

10

  • 2

10

  • 1

10 10

1

ID (µA/µm) VGS (V)

Off-state Current

Lg = 1 µm Wf = 100  14 nm

HSQ InGaSb AlGaSb

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SLIDE 42

42

  • 0.6
  • 0.4
  • 0.2

0.0 0.2 0.4 0.6 10

  • 3

10

  • 2

10

  • 1

10 10

1

ID (µA/µm) VGS (V)

No InGaSb channel

Off-state Current

Lg = 1 µm Wf = 100  14 nm Buffer leakage contributes substantially to off current

AlGaSb HSQ InGaSb AlGaSb

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SLIDE 43

43

Record gm = 268 μS/μm at Wf = 46 nm

Benchmark

Normalized by conducting width

50 100 150 200 100 200 300

gm (µS/µm) Wf (nm)

This work

MIT CSW ’17 MIT IEDM ’15

FinFETs Planar

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SLIDE 44

44

Benchmark

Normalized by conducting width Normalized by Wf

Planar FinFETs This work

50 100 150 200 200 400 600 800

ddd ddd

gm/Wf (µS/µm) Wf (nm)

If normalized by footprint, gm = 704 μS/μm at Wf = 10 nm

50 100 150 200 100 200 300

gm (µS/µm) Wf (nm)

This work

MIT CSW ’17 MIT IEDM ’15

FinFETs Planar

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SLIDE 45
  • Studied sidewall cleaning of InGaSb FinFETs

‒ III-Sb-compatible digital etch ‒ Etching rate = 2 nm/cycle ‒ Mitigation of surface leakage

  • Demonstrated most scaled InGaSb p-channel FinFETs

‒ Minimum Wf = 10 nm ‒ Record device performance ‒ Improved subthreshold performance

  • Face challenge: to improve turn-off characteristics

45

Conclusions