SLIDE 25 Phase-2 New Readout Architecture
Optical Links
Phase-II Upgrade Front-End Board
Preampl. Layer Sum Boards [LSB] CLK Fanout Linear Mixer
Shaper
Baseplane
Phase-II Upgrade ROD DAQ
Output OTx
Controller Board
Timing Trigger Control Distribution
80-100m fibers
TTC Partition Master ADC ADC
Optical Links
ADC
MUX/Serializer (FPGA)
ADC
Optical Receiver Deserializer Timing Trigger Control Rx
FPGA SDRAM L0 Trigger Processor
Ped Sub Ped Sub Ped Sub Ped Sub E,t N-tap FIR E,t N-tap FIR E,t N-tap FIR E,t N-tap FIR
480 Gbps/module 1.92 Tbps/board ~250 Gbps/board
L1 Trigger Processor LAr Trigger Digitizer Board (LTDB)
Crate Monitoring
Tower Builder Board [TBB]
iS(t- i)
Trigger Tower Sum and Drivers
PZ+Dly ADC & Gain Selec. MUX/Serializer
FPGA L1-buffers
Ped Sub Ped Sub Ped Sub Ped Sub E,t N-tap FIR E,t N-tap FIR E,t N-tap FIR E,t N-tap FIR
L0 Accept Logic & L1 Trigger Feature Extractor
Monitoring Stations Level-0,1 Calorimeter Trigger System
L1 Accept Logic
L0-pipelines
ADC & Gain Selec. ADC & Gain Selec. ADC & Gain Selec. 2,3 Gains ORx Arrays OTx OTx CLK & Cfg. CLK Fanout ORx
LAr Detector Inputs Digital Processing System (DPS)
New Backend able to handle 150 Tbps New FEBs to sam- ple and digitize continuously at 40 MHz Provide input to new, fully digital L1 trigger system
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Phase-1 upgrades used to create new Level-0 trigger
sice) ATLAS LAr performance and upgrade INSTR14, Novosibirsk 25 / 29