Readout Electronics Upgrades of the ATLAS Liquid Argon Calorimeter - PowerPoint PPT Presentation

Readout Electronics Upgrades of the ATLAS Liquid Argon Calorimeter Christopher Anelli on behalf of the ATLAS experiment Pisa Meeting on Advanced Detectors, June 2, 2018 University of Victoria

High Luminosity LHC Phase-II Upgrade and HL-LHC: • 7.5·10 -34 cm -2 s -1 peak luminosity. • 25 ns bunch spacing (40 MHz) • Expected integrated luminosity of 4000 fb -1 (over ~12 years) • Up to 200 average minimum bias events per bunch crossing • Increased radiation damage to detector Pisa Meeting 2018 Christopher Ryan Anelli 2

Liquid Argon Calorimeter Sampling Calorimeters • EMB : LAr - Lead, | η | < 1.475 • EMEC : LAr - Lead, 1.375 < | η | < 3.2 • HEC : LAr - Copper, 1.5 < | η | < 3.2 • FCAL : LAr - Copper, 3.1 < | η | < 4.9 . and LAr - Tungsten • 182,500 channels. • The layers of each module have different granularities. • Largest fraction of energy deposited in middle layer. (EM Calo) • Fine granularity used to reconstruct incident particle’s direction. Pisa Meeting 2018 Christopher Ryan Anelli 3

Pulse Shaping readout electrode absorber • High energy particles shower in the calorimeter, ionizing the LAr. outer copper layer (~2 mm) inner copper layer • HV readout electrodes placed kapton between grounded absorbers. outer copper layer liquid argon gap liquid argon gap • Drift gap of 2.1 mm corresponding to stainless steel electron drift time of 450 ns glue (for EM Calo) lead HV HV • Drift electrons induce triangular pulse, amplitude proportional to deposited energy. • Pulse passed through Bipolar CR -(RC) 2 filter, with programmable shaping time. (baseline 13 ns) • 25 nano-second sampling. For more details checkout the LAr Calorimeter Performance talk by Stefanie Morgenstern Pisa Meeting 2018 Christopher Ryan Anelli 4

Upgrade Motivation Technical Motivations: Preserving physics reach (ie Higgs) for higher data taking rates requires updated triggers: • Current readout electronics are incompatible with new Trigger System. Upgraded triggers require higher trigger rate (1MHz), longer latency, and higher granularity calorimeter information. • Existing front-end electronics will reach the limit of their radiation tolerance before the end of the HL-LHC. Performance Example: Simulation shows upgraded ATLAS detector can maintain sensitivity to golden, H-> γγ channel. Optimistic scenario: increased statistics reduce global constant term to design value, 0.7%. Pessimistic scenario: term remains same as 2015, 1% barrel and 1.4% endcap . a ⊕ b σ E E ⊕ c √ E = E Pisa Meeting 2018 Christopher Ryan Anelli 5

� � � � � Phase-II Readout Electronics Existing readout electronics will be completely replaced: Front-End • Pulse shaping optimized to minimize Calibration Board FELIX DAC Clock & Control total noise. LAr Signal Processor (LASP) TTC Control Phase-II Upgrade • New calibration board. FPGA Front-End Board (FEB2) 2 gains Ped E,t Shaper Sub N-tap FIR Clock & Control ADC x2 data buffers Ped E,t • Full granularity, each Sub N-tap FIR ADC OTx x2 x2 FELIX ... Ped E,t Array MUX/Serializer LAr Calorimeter Cells Sub N-tap FIR ORx cell is digitized and ADC x2 Arrays Ped E,t Sub N-tap FIR ADC x2 sent to the backend. L0/L1 Preampl. 75 m Optical Accept Linear Energy sums & Links fibers Logic Mixer Data reduction Off Detector CLK OTx OTx Fanout Array Array Layer Sum Boards [LSB] • New, LAr Signal Baseplane L0/L1 Central Trigger Processor Processor (LASP) LAr Trigger Digitizer Board (LTDB) board to process LAr Digital Processing System (LDPS) Global Event Ped E,t FPGA digitized inputs and Sub N-tap FIR ADC Processor Ped E,t Sub N-tap FIR ADC Optical Receiver output energy and MUX/Serializer Optical Links Deserializer (FPGA) Ped E,t Sub N-tap FIR ADC ~250 Gbps/board FEX timing information. Ped E,t 480Gbps/module Sub N-tap FIR 1.92 Tbps/board ADC CLK Fanout SDRAM Timing Crate Trigger • Information is sent ORx Monitoring Level-0,1 Calorimeter Trigger Control Rx System from the LASP to new, FELIX L0 Triggers. Pisa Meeting 2018 Christopher Ryan Anelli 6

Front-End Design The Front-end board has separate ASICs for the Preamp/Shaper, Digitization, Serialization, and Optical Transmission: Pisa Meeting 2018 Christopher Ryan Anelli 7

Preamplifier / Shaping ASIC The Preamplifier and Shaping will be implemented on a single ASIC. • 65 nm and 130 nm CMOS prototypes have both been explored. vdd� _PA� 130 nm 65 nm Rf� (dynamic range)� SW_HG_to_� LG� =�Antisaturation� out_PA_HG� R • Line terminating preamplifier • Fully differential preamplifier R0� Zin�_� SCG� Super Common Gate� v i = -v o /N - v o + i nR i i - Low noise Voltage Amplifier� -v o • Linearity better than 0.5%, • Linearity better than 0.2%, + G = -�C1�/� C2� C1� C -v o /N in_PA� out_PA_� LG� up to 7 mA. up to 10 mA. C2� C·(N-1) SC0� SC7� Ci� Both designs will be merged into one 130nm chip. Pisa Meeting 2018 Christopher Ryan Anelli 8

Digitization The LAr cell’s electronic noise must be less than MIP signal. Requiring ADC’s least significant bit (LSB) value to be less than electronic noise leads to a dynamic range 16 bits wide. • Readout electronics utilize 14 bit ADCs. • To cover 16 bit range a two gain system is utilized. • Energy of gain switching chosen so photons from H → γγ , have the same gain as electrons from Z → ee (used for energy scale calibration.) Pisa Meeting 2018 Christopher Ryan Anelli 9

ADC Digitization handled by 40 MHz,14 bit, radiation hard, ADC. ASIC consists of: Dynamic Range Enhancement block (+2 bits), DRE. • Successive Approximation Register block, SAR. • • Have tested ENOB at 20 MSPS. • Digitization of simulated pulses by the ADC. • Commercial ADC IP blocks may be available for purchase. Pisa Meeting 2018 Christopher Ryan Anelli 10

LASP In the back-end, Phase-II Upgrade introduces new LAr Signal Processor (LASP) based on FPGA technology: • Processes digitized waveforms from each of the calorimeter cells. • Digital filtering algorithms to calculate energy and timing of LAr pulse. • Interfaces to L0, hardware triggers and Data Acquisition (DAQ). • Buffer data while awaiting trigger decision. FELIX / DAQ L0A/ fragment builder TTC L1A raw data precision FEX data L0 data data buffer buffer buffer buffer gain sel. configurable input stage FEXes remapping front-end energy pulse summing processing GlobalEvent summing energy data controller reduction Pisa Meeting 2018 Christopher Ryan Anelli 11

LASP Module Each LASP module contains two LASP units each with it’s own processing FPGA: • LASP board design is based on Advanced Telecommunication Computing Architecture (ACTA) • Each unit includes elector-optical receiver and transceiver arrays. • FPGA takes inputs from up to 4 FEBs, covering 448-512 calorimeter cells. • A test board is being developed based on the Intel Stratix 10 FPGA. LASP 48-link MPO 12 Rx 12 Rx 12 Rx 12 Rx 12 Rx Desire reliability: so LASP Main Blade 12 Tx 48-link MPO Connector 11G 11G 11G 11G 11G RTM 11G processors will not need to 12 Tx MMC 12 Tx 11G DDR3 Processing 48-link MPO 11G be replaced over 10+ years 12-link MPO FPGA Flash 4 Tx • Flash 12 Tx 25G of operation. DCDC DDR3 Clock 11G • 48-link MPO 12 Rx 12 Rx 12 Rx 12 Rx Clock 12 Tx Connector • 11G 11G 11G 11G Main Base 11G FPGA LASP Unit 12 Rx 11G 48-link MPO 12 Rx 12 Rx 12 Rx 12 Rx 12 Rx 11G 11G 11G 11G 11G Ethernet QSFP Switch 12 Tx MMC 11G DDR3 Processing 48-link MPO • Connector Base FPGA 4 Tx • Flash 25G IPMC DCDC • 48-link MPO 12 Rx 12 Rx 12 Rx 12 Rx Clock • 11G 11G 11G 11G DCDC Stratix 10 Development Kit LASP Unit LASP RTM Pisa Meeting 2018 Christopher Ryan Anelli 12

Digital Filtering Algorithms *Only 4 samples used since Run-2 OFC • Current digital filtering algorithm uses optimal filtering coefficients (OFC) , to extract each cell’s energy and timing information. • In some cases, other algorithms such as the Wiener Filter , may better suppress the pileup noise. Studies are ongoing. 2500 Total Noise [MeV] ATLAS Simulation Internal OF 2000 WFFC 1500 1000 500 0 O O O O O F F F F F C C C C C , , , µ , , = µ µ 0 20 = 80 = 140 µ 200 µ 0 = = 2 8 1 2 0 0 4 0 0 0 Pisa Meeting 2018 Christopher Ryan Anelli 13

Trigger Bandwidth LAr Calorimeter interfaces with the L0 (L1) triggers: • Data bandwidth and links to the FPGA depends on the number of cells transmitted to the trigger. • For the L0 global trigger, an energy threshold of 2 times the cell noise, 2 σ , is applied. • For 2 σ threshold ~5.5% of cells are normally transmitted. • However, high energy particles or noise bursts can cause individual FPGAs to transmit a significantly greater fraction of cells. • Planned bandwidth sufficient to transmit 30% of cells, ~153. • Also requires bit pattern (512 bits) reflecting which cells are above threshold. • Total per LASP module bandwidth to the L0 Global Trigger is expected to be 102.4 Gbps. Pisa Meeting 2018 Christopher Ryan Anelli 14