Development of ATLAS Liquid Argon Calorimeter Readout Electronics - - PowerPoint PPT Presentation

Development of ATLAS Liquid Argon Calorimeter Readout Electronics for the HL-LHC

Maximilian Hils,

• n behalf of the ATLAS Liquid Argon Calorimeter Group

Institut für Kern- und Teilchenphysik, Technische Universität Dresden

May 24, 2017 Technology and Instrumentation in Particle Physics 2017, Beijing, China

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Large Hadron Collider

Proton-proton collisions with √s = 14 TeV at a rate of 40 MHz About 1011 protons per bunch resulting in a design luminosity of 1034 cm−2s−1

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ATLAS Detector

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ATLAS Liquid Argon Calorimeter

Sampling calorimeter (absorber: Pb, Cu, W; active: LAr) 182 468 detector cells arranged in layers

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HL-LHC Upgrade Plans

Right now, the mean number of p-p collisions per bunch crossing is 20 After the phase-2 upgrade (2024–26), up to 200 expected

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Performance Requirements on the Readout Electronics

Currently installed readout is not ready for HL-LHC Large number of pile-up events will challenge the trigger system

Hardware trigger rate up to 1 MHz 60 µs data buffering Currently installed front-end electronics cannot provide that

All 1524 front-end boards and the back-end electronics need to be replaced

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Upgrade of Readout Electronics

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Upgrade of Readout Electronics

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Upgrade of Readout Electronics

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Specifications for the Front-end Electronics

Preamplifiers have a finite dynamic range [30 MeV-4 GeV] Lineary of 0.1 % for energies up to 10 % of the dynamic range required Noise level below intrinsic calorimeter resolution Either two gains with 14-bit ADCs or three with 12-bit ADCs

Energy [GeV]

• 2

10

• 1

10 1 10

2

10

3

10

4

10 (E)/E [%] σ

• 3

10

• 2

10

• 1

10 1 10

2

10

0.2% ⊕ E/GeV 10%/ 14 bit range and 12 bit resolution; gain = x1/x30 12 bit range and resolution; gain = x1/x5/x50

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Preamplifier & shaper

Preamplifier and shaper will be implemented in a single ASIC Low noise required Low power required Two R&Ds paths on-going:

65 nm CMOS, test chips submitted April 2017 130 nm CMOS, tests chips submitted September 2016

The 65 nm CMOS is a fully differential preamplifier

Fully‐Differential Amplifier with Passive Feedback R

‐

vo vi = ‐vo/N + + ‐ ‐vo

inR

ii ‐vo/N

C

• R‐noise 4kT/R

C∙(N‐1)

• Input impedance +R/(N+1)

positive positive

• Fully‐differential output

Figure: Post-layout simulations and architecture view of the 65 nm ASIC

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Preamplifier & shaper: 130 nm Prototype

New electronically cooled preamp design Linearity ∼ 0.1 %, within 1 % up to 7 mA In general, good agreement with simulations, except noise Issue understood, new prototype in 2017

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Analog-to-digital Converter

Commercial and custom solutions ADC needs to be interfaced to CERN lpGBT serializer Custom design in 65 nm of a 14-bit ADC:

12-bit Successive Approximation Register (SAR) and Dynamic Range Enhancer (DRE)

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Analog-to-digital Converter

Commercial off-the-shelf (COTS) ADCs:

Twenty 14-bit and seven 16-bit ADCs reviewed 16-bit candidate ADCs identified (based on performance and cost) Irradiation tests planned for 2017

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Back-end Electronics

About 35 000 optical links from the front-end Input data rate of 275 Tbps About 400 high-performance FPGAs are needed

energy summing

L0A/ L1A

input stage configurable remapping pulse processing precision data buffer controller TTC L0Global front-end FELIX / DAQ FEXes fragment builder raw data buffer

gain sel.

energy summing data reduction FEX data buffer L0 data buffer

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ATLAS Readout Electronics Upgrade Simulation

Optimization of the readout chain with AREUS Comparison of e.g. deposited and reconstructed energies

Relative Frequency / 0.5 GeV / 0.0 GeV

6 −

10

5 −

10

4 −

10

3 −

10

2 −

10

1 −

10 1 [GeV]

Depo T,EC

E 10 20 30 40 50 60 70 [GeV]

Depo T,EC

• E

Reco T,EC

E 3 − 2 − 1 − 1 2 3

Absolute Error Correlation , Electrons

Max

= 14TeV, EM Middle, OF s

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Summary

Front-end and back-end electronics need to be replaced due to higher pile-up Investigating different architectures for the preamplifier & shaper, test chips already submitted Studies of custom and commercial ADC designs Simulation studies for the readout electronics on-going

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Backup

Radiation tolerance requirements for the front-end electronics

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Backup

AREUS

104 105 106 107 108 109 1010 Frequency [Hz] 10-14 10-12 10-10 10-8 10-6 10-4 10-2 100 102 Power [nV²/Hz] EMB Middle Layer (η=0.0125) electronics noise

Preamp = 50 HG τshape = 13 ns σRMS = 24.0 µV

100 200 300 400 500 600 700 Time [ns] 0.10 0.05 0.00 0.05 0.10 0.15 Voltage [V]

EMB Middle Layer ( =0.0125) pulse shapes ET = 100.0 GeV ET = 200.0 GeV ET = 400.0 GeV Preamp = 50 HG τshape = 13 ns

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