Multiple Gate CMOS and Beyond Dept. of EECS, KAIST Yang-Kyu Choi - - PowerPoint PPT Presentation

Multiple Gate CMOS and Beyond

• Dept. of EECS, KAIST

Yang-Kyu Choi

2

Outline

• 1. Ultimate Scaling of MOSFETs
• 3nm Nanowire FET
• 8nm Non-Volatile Memory Device
• 2. Multiple Functions of MOSFETs
• 3. Summary

3

CMOS Evolution Scenario

Bulk-single gate

S D G S D G

SOI single gate Double gate Ω-gate All-around

Fin Fin Fin

Buried Oxide

LG=4nm NEC IEDM 2003 LG=8nm IBM IEDM 2003 LG=10nm AMD/Berkeley IEDM 2003 LG=10nm LETI VLSI 2005

No report for Sub-50nm

This Work

4

ITRS Roadmap

DG Bulk SG LG (nm) Isd,leak (µA/µm) Id,sat (mA/mm) 2006 2008 2011 1.1 0.9 0.5 28 22 16 0.15 0.2 1130 1570 Solution exist Solution being pursued

Source: ITRS 2005 roadmap

EOT (nm) DG Bulk SG DG Bulk SG 0.11 0.6 2013 13 2220 0.5 2020 2981 0.11 0.1 0.8 0.32 2490 1899 No known solution 5

5

All-Around Gate (AAG) FinFET

• To fabricate sub-5nm silicon transistor,

All-Around Gate (AAG) FinFET was proposed.

Gate

Drain Source Gate

• AAG-FinFET

– LG=3nm – WFin=3nm – EOT(HfO2)=1.2nm

6

Process Flow of AAG-FinFET

• (100) SOI wafer
• Silicon body thinning
• Fin patterning (dual-resist)
• Sacrificial oxidation
• Gate dielectric (HfO2)
• Poly-silicon deposition
• Gate patterning (dual-resist)
• Spacer formation
• Source/Drain implantation
• Spike annealing (1000oC)
• Forming gas annealing

(450oC)

7

Buried oxide

Poly-si 3nm 5nm 3nm S 5nm 20nm HfO2 Silicon fin

3nm AAG FinFET: Silicon-Fin

Gate

Drain Source Gate

Gate

Drain Source Gate

Y.-K. Choi et al., VLSI, 2006

8

5nm

Silicon fin

Poly-si Gate

5nm 5nm Poly-si HfO2 Si IFO HfO2 IFO Si

Poly-si

Gate

Drain Source Gate

Gate

Drain Source Gate

5nm 3nm

3nm AAG FinFET: Gate

9

• Large DIBL and SS due to thick EOT

– ITRS requirement: 0.5nm EOT for DG

• 1.0
• 0.6
• 0.2

0.2 0.6 1.0 10

• 7

10

• 6

10

• 5

10

• 4

10

• 3

Simulated Measured

Transconductance [µS/µm]

VD=1.0V VD=0.2V

DIBL=230mV/V SS=208 mV/dec HfO2 =1.4nm LG=3nm WFin=3nm

Drain Current [A/µm] Gate Voltage [V]

20 40 60 80 100 120 140 160

0.0 0.2 0.4 0.6 0.8 1.0 50 100 150 200 250 300 350 HfO2 =1.4nm LG=3nm WFin=3nm

VG=0.2V 0.4V 0.6V Drain Current [µA/µm] Drain Voltage [V]

I-V of 3nm AAG FinFET

10 10

• Device scaling limit (Operating at 300K)

– Heisenberg’s uncertainty principle – Shannon - von Neumann - Landauer (SNL) expression

) 300 ( 5 . 1 2 ln 2 2

min

K T nm T k m E m p x

B c bit c

= = = = ∆ = h h h

Fabricated 3nm all-around gate FinFET is approaching to this fundamental limit.

1.5

SCALING LIMIT

Fundamental Limit of Scaling

11 11

Nanowire Structure

Buried Oxide Si Poly-silicon

Nitride trap layer Blocking oxide Tunneling oxide

• Silicon nanowire non-volatile memory

structure for ultimate scaling

8nm Non-Volatile Memory Omega-shape gate ONO-structure

12 12

8nm Si Nanowire NVM

Gate

BOX Poly-silicon Gate trap sites O S NO

e-

S

10nm Silicon Nanowire (7/10nm) Tunneling oxide Nitride trap layer Blocking oxide Poly-silicon

Y.-K. Choi et al., VLSI, 2007

13 13

8nm Si Nanowire NVM

3.8nm 6.4nm 5.1nm Gate

Oxide Nitride Silicon 7/10nm 3.8nm 6.4nm 5.1nm

8nm TONO=15nm > LG=8nm

14 14

8nm Silicon Nanowire NVM with ONO

• 4
• 3
• 2
• 1

1 2 3 10

• 10

10

• 9

10

• 8

10

• 7

10

• 6

1x10

• 5

1x10

• 4

ONO=3.8/6.4/5.1nm tProgram=80µsec LG=8nm WNW=7nm HNW=10.5nm 8V 10V VPG=12V Initial

Drain Current [A/µm] Gate Voltage [V]

• 3
• 2
• 1

1 2 3 10

• 10

10

• 9

10

• 8

10

• 7

10

• 6

1x10

• 5

1x10

• 4

LG=8nm WNW=7nm HNW=10.5nm

• 8V
• 10

VER=-12V Initial ONO=3.8/6.4/5.1nm tErase=80µsec

Drain Current [A/µm] Gate Voltage [V]

• 8nm LG with 7nm WNW using ONO-structure
• Acceptable electrical performance by omega-gate
• Wide hysteresis shows the probability of multi-level NVM

15 15

0.0 0.5 1.0 1.5 2.0 2.5 3.0

LG=8nm WNW=7nm HNW=10nm

• 10V

VER=-8V VER=-12V

10

• 8 10
• 7 10
• 6 10
• 5 10
• 4 10
• 3 10
• 2 10
• 1 10

0 10 1

∆VT [V]

Erase Time [sec]

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

ONO=3.8/6.4/5.1nm LG=8nm WNW=7nm VPG=12V VPG=8V VPG=10V

10

• 8 10
• 7 10
• 6 10
• 5 10
• 4 10
• 3 10
• 2 10
• 1 10

0 10 1

∆VT [V]

Program Time [sec]

8nm Si Nanowire Memory

• 8nm NVM: VT window = 2V

– Program @ +12V/1msec, Erase @-12V/1msec

16 16

Scaling Limit in NVM

• Ultimately scaled NVM
• Nanowire + SONOS
• Close to end-point of semiconductor memory

Y.-K. Choi et. al., VLSI 2007

TO/N/O=15nm > Lg=8nm

Scaling Limit !

17 17

We are here We are here

Where to Go?

Multi-Bit Multi- Functioning

This Work !

Down Scaling

18 18

• Increased volume
• Complexity in assembly
• Chip-to-chip interference

Example of Fusion Memory

(System in Package)

DRAM DRAM NVM NVM SRAM SRAM

. . .

Wafer level fusion !!

19 19

Principal of SONOS Flash Memory

Gate

Substrate

S D

⊖ ⊖ ⊖ ⊖ ⊖ ⊖ ⊖ ⊖ ⊖ ⊖ ⊖ ⊖

control oxide tunnel oxide nitride

Gate

Substrate

S D

⊕ ⊕ ⊕ ⊕ ⊕ ⊕ ⊕ ⊕ ⊕ ⊕ ⊕ ⊕

< program > < erase >

Gate

Substrate

S D

⊖ ⊖ ⊖ ⊖ ⊖ ⊖ ⊖ ⊖

Gate

Substrate

S D

⊕ ⊕ ⊕ ⊕ ⊕ ⊕ ⊕ ⊕

< read ‘0’ > < read ‘1’ > ‘1’ ‘0’

Gate voltage Drain current

• High density ↑
• Non-volatile ↑
• Speed ↑

Features of flash

20 20

Principal of Capacitorless DRAM

Source : IEEE spectrum Dec. 2008 Source : IEEE spectrum Dec. 2008

Gate

Substrate

S D

⊖

< program > Buried oxide

⊖ ⊕ ⊕ ⊕ ⊕ ⊕

Gate

Substrate

S D

< erase > Buried oxide

⊕ ⊕ ⊕ ⊕ ⊕

Gate

Substrate

S D

< read ‘1’ > Buried oxide

Gate

Substrate

S D

< read ‘0’ > Buried oxide

⊕ ⊕ ⊕ ⊕

• High speed ↑
• 2x denser than 1T/1C

DRAM ↑

• 5x denser than SRAM ↑
• Volatile ↓

Features of 1T-DRAM

‘0’ ‘1’

Time Drain current

21 21

capacitorless 1T-DRAM erase

Basis of URAM Operation (1)

Gate voltage Drain voltage flash program flash erase capacitorless 1T-DRAM program

• Program : Impact ionization
• Erase : Forward junction

current (Low gate & drain voltage)

Flash Memory Mode

• Program : FN tunneling/HEI
• Erase : FN tunneling/HHI

(High gate & drain voltage)

Capacitorless 1T-DRAM Mode Disturbance Issue

• Periodical refresh

22 22

드레인

Source Drain Gate Quantum Barrier

DRAM Flash Memory

electron

hole

Oxide Nitride Oxide

Multi-Function (URAM) Operation

23 23

Family of URAM

• S. Okonin et.al.,

SOI conf., 2001

• R. Ranica et.al.,

VLSI symp., 2004

24 24 Si:Ge Si Si substrate Si substrate n-well Si Si substrate Si:C Si Si substrate Buried oxide Si

Process Flow (1)

SOI Substrate SOC Substrate SON Substrate SOG Substrate

• Initial SOI substrate
• Initial bulk substrate
• Si:C epitaxial growth
• Si epitaxial growth
• Initial bulk substrate
• Buried n-well implantation
• p-body implantation
• Initial bulk substrate
• Si:Ge epitaxial growth
• Si epitaxial growth

25 25

Puntch stop implantation Active fin lithography Photoresist trimming Fin patterning

SiO2 SiO2 Si substrate Hole barrier layer fin SiO2 SiO2 Si substrate Hole barrier layer fin

Process Flow (2)

Si substrate Hole barrier layer fin

HDP oxide deposition Oxide CMP Oxide recess formation

26 26

Gate patterning S/D implantation Activation Forming gas annealing O/N/O formation Poly-Si deposition

SiO2 SiO2 Si substrate Gate Hole barrier layer fin SiO2 SiO2 Si substrate Gate Hole barrier layer fin SiO2 SiO2 Si substrate Gate Hole barrier layer fin SiO2 SiO2 Si substrate Gate Hole barrier layer fin

Process Flow (3)

27 27

URAM on SOI

28 28

Cross sectional view of URAMs

URAM

• n SOI

URAM

• n SiC

URAM

• n

Buried N-well URAM On SiGe

29 29

• 1.0
• 0.5

0.0 0.5 1.0 1.5 2.0 10

• 11

10

• 10

10

• 9

10

• 8

10

• 7

10

• 6

10

• 5

SOI SOC SOG SON VD = 1V Drain current, VD (A) Gate voltage, VG (V)

ID-VG Characteristics

• Superior device performances are result of the 3D nature.

ID

30 30

ID-VD Characteristics (Kink)

SOI SOC SON SOG

31 31

Program

P/E in NVM

Erase

• P/E sensing windows are acceptable.

32 32

Reliability in NVM

Retention Endurance

• Data retention and endurance are acceptable.

33 33

PD URAM FD URAM

50 100 150 200 10 20 30 40 50 60 70 80 ∆Is=20µΑ

Conventional FinFET SONOS SOI URAM 80msec

∆Is=7µΑ

Source current, IS (µA) Time, t (msec)

Capacitorless 1T-DRAM in SOI

< Potential Profile > < Measurement Results >

0.8V 0.7V 0.6V

Y.-K. Choi et. al., IEDM 2007

• Proposed SOI URAM exhibits wider sensing current window.

34 34

bulk MOSFET SON URAM

Capacitorless 1T-DRAM in SON

1 2 3 4 5 4 8 12 16 20 24 28 32 VSUB=0.5V VSUB=0V VSUB=0.3V

∆IS=4µA ∆IS=7µA Time, t (msec)

Sensing current, IS (µA)

< Excess Hole Concentration > < Measurement Results >

• Capacitorless 1T-DRAM works in SON floating substrate.

Y.-K. Choi et. al., VLSI 2008

35 35

SON URAM SOC URAM

< Excess Hole Concentration > < Measurement Results >

1 2 3 4 5 6 4 8 12 16 20 24 28

VSUB=0.3V VSUB=0V

∆IS=11µA ∆IS=7µA

Time, t (msec) Source current, IS (µA)

Capacitorless 1T-DRAM at SOC

• Capacitorless 1T-DRAM works in SOC floating substrate.

Y.-K. Choi et. al., VLSI 2008

36 36

Summary

IT only NT only NT⊗IT

• 3nm MOSFET and 8nm non-volatile memory device were

demonstrated. → Close to scaling limit.

• Multi-function URAM was demonstrated.

→ Continuously increased density

37 37

Simulation Result of Energy Band

Built-in Potential for Buried n-well

SIMS profile of the buried n-well

0.9 eV

• Built-in potential confines excess holes.

38 38

• 3.0
• 2.5
• 2.0
• 1.5
• 1.0
• 0.5

0.0 0.5 0.0 0.2 0.4 0.6 0.8 1.0 Si/Si0.94C0.06/Si Si/Si0.7Ge0.3/Si

Normalized capacitance

Gate voltage, VG (V)

• Double slopes appear in weak accumulation region.

∆EV=-180 meV ∆EV= 200 meV

Band-Offset for Si:C & Si:Ge (2)

C-V for Band Engineered Substrate Energy Band Diagram

39 39

Scaling Issue

(Why capacitorless DRAM?)

µ-processor Cache memory SRAM (32F2) 50% in 2006

• Capacitorless DRAM is a promising candidate for

embedded memory. 83% in 2008 90% in 2011

Is this memory or µ-processor ? Cache portion

• Cell capacitance in DRAM > 25fF (non-scalable)

Cell area (~8F2) is continuously reduced.

40 40

capacitorless 1T-DRAM erase Gate voltage Drain voltage flash program capacitorless 1T-DRAM program

Disturbance Issue

• Periodical refresh

Soft-Program Issue

1T-DRAM mode Initialization :

Set VT of all cells to 0.2V by adjustment of trapped charges

Capacitorless 1T-DRAM operation Verification VT=0.2V? yes no refresh

41 41

GIDL Program Method

200 400 600 800 1000 20 40 100 nsec 100 nsec 12µA Source current, IS (µA) Time, t (µsec)

• 2
• 1

1 2 Drain voltage Gate voltage Bias (V) 10 10

1

10

2

10

3

10

4

10

5

0.3 0.4 0.5 0.6 GIDL program VG=-2V, VD=2V Impact ionization program VG=1, VD=2V Threshold voltage, VT (V) Stress time, t (sec)

Impact ionization GIDL

[J.-W. Han et. al., EDL, Apr. 2009]

< Soft-program test > < 1T-DRAM Measurement >

• GIDL program method mitigates soft-programming.

42 42

G-to-S/D Underlap Structure

Substrate

S D

Buried oxide

Gate

Substrate

S D

Buried oxide

Gate

50nm Gate Buried oxide S D junction

[J.-W. Han et. al., EDL, May 2009]

⊖ ⊖ ⊕ ⊖ ⊖ ⊕

G-to-S/D Overlap G-to-S/D Underlap

43 43

0.0 0.5 1.0 10 20 30 40 50 G-to-S/D overlap G-to-S/D underlap 8 µA 11 µA Source current, IS (µA/µm) Time, t (msec)

• 2
• 1

1 2 3 50 nsec 50 nsec VD VG Bias (V) 10 10

1

10

2

10

3

10

4

10

5

0.15 0.20 0.25 0.30 0.35 0.40 0.45 Stress bais : VG=1V, VD=2.5V G-to-S/D underlap G-to-S/D overlap Threshold voltage, VT (V) Stress time, t (sec)

G-to-S/D Underlap Structure

[J.-W. Han et. al., EDL, May 2009]

< Soft-program test > < 1T-DRAM Measurement >

• G-to-S/D underlap structure mitigates soft-programming.

44 44

10 20 30 40 50 60

• 40
• 20

20 40 60 80 100 120

∆IS=11µA ∆IS,HfO2=55µA ∆IS,SiO2=20µA

read hold erase hold read

underlap with SiO2 spacer underlap with HfO2 spacer

• verlap with

SiO2 spacer

Source current (µA/µm) Time (nsec)

Issue and Solution of G-to-S/D Underlap Device Structure

[J.-W. Han et. al., EDL, May 2009]

Substrate

S D

Buried oxide

Gate

Substrate

S D

Buried oxide

Gate

SiO2 High-k

< Simulation Results >

SiO2 Spacer High-k Spacer

• High-k spacer countervails the parasitic series resistance
• f the G-to-S/D underlap.