Ultra-Thin Body Self-Aligned I nGaAs MOSFETs on I nsulator (I I I - - PowerPoint PPT Presentation

Ultra-Thin Body Self-Aligned I nGaAs MOSFETs on I nsulator (I I I -V-O-I ) by a Tight-Pitch Process

Jianqiang Lin Lukas Czornomaz*, Nicolas Daix*, Dimitri A. Antoniadis, and Jesús A. del Alamo

Microsystems Technology Laboratories, MIT * IBM Zurich Research Laboratory June 22, 2014

Sponsors:

• FCRP-MSD Center
• MIT Donner Chair
• MIT SMA and SMART programs
• Project Marie Curie FP7-PEOPLE-2011- IEF-300936 LATICE

Motivation

• Superior electron transport properties in InGaAs channel

[J. del Alamo, Nature 2011]

In0.7Ga0.3As HEMTs Strained Si VDS=0.5 V Si VDS=1.1-1.3 V

2 2

Si/III-V Integration

UC Berkeley [K. Takei, APL 2013] U Tokyo [S. Kim, IEDM 2013] AIST [T. Irisawa, IEDM 2013]

Lc=150 nm

Contact

Gate n+

BOX p-type Si

MIT / IBM [This work]

3

Substrate Fabrication

Channel: In0.7Ga0.3As

BOX: Al2O3

• 1. MBE growth

n+ cap Protection layer: InGaAs Device layers Stopper: InP Buffer: InAlAs Si δ-doping: 1x1012 cm-2

BOX p-Si BOX p-Si

Device layers H+ InP buffer/wafer InP buffer/wafer

• 2. H+ implants & Al2O3 depo

BOX p-Si

InP H+ H+

• 3. Wafer bonding

Following Czornomaz, IEDM 2012

• 4. Thermal split
• 5. InP etch back

4

Substrate Fabrication

• Smooth surface of final

substrate

2 µm

RMS= 0.25 nm

3 nm

5

BOX p-Si

Device layers

• Final substrate

Device Fabrication

• 2. Gate opening,

Mesa isolation

• 4. Gate oxide ALD
• 5. Gate metal
• 6. Pad formation

Channel n+ Cap p-Si W/Mo SiO2 Mo HfO2 Pad Ledge

• 1. Ohmic/Oxide deposition
• 3. 3-step gate recess,

Damage anneal

BOX

Following Lin, IEDM 2013

6

Final Device Structure

M1 n+ cap W/Mo InGaAs Buffer Al2O3 p-Si Mo HfO2 SiO2

LLedge

7

• Gate dielectric HfO2=3.5 nm, EOT=0.7 nm
• Intrinsic channel In0.7Ga0.3As= 8 nm
• BOX Al2O3 = 30 nm

Lc=150 nm

Contact

Gate n+

BOX p-type Si

BOX Mo Gate n+ Mo Contact Buffer HfO2 Channel Lg=50 nm Lledge=30 nm

TEM Cross Sections

p

• Process enables:
• Tight pitch: Lp=150 nm
• Precise control of ledge:

Lledge=30 nm

8

Characteristics of Lg = 70 nm MOSFETs

0.0 0.2 0.4 0.6 50 100 150 200 250

Vgs-Vt=0 to 0.8 V in 0.2V step Lg=70 nm

Id (µA/µm) Vds (V)

• 0.4

0.0 0.4 0.8 100 200 300 400 gm (µA/µm) Vgs (V)

Vds=0.5 V Lg=70 nm

• 0.4

0.0 0.4 0.8 10

• 10

10

• 9

10

• 8

10

• 7

10

• 6

10

• 5

10

• 4

Id (A/µm) Vgs (V)

Vds=0.05 and 0.5 V Lg=70 nm

FOM at Vds=0.5 V

• gm,pk = 309 μS/μm
• Vt = 96 mV
• S = 140 mV/dec
• DIBL = 80 mV/V
• Rsd = 1050 Ω.μm

9

I mpact of Back Bias

0.0 0.2 0.4 0.6 50 100 150 200 250

Vbs= 3 V

Id (µA/µm) Vds (V) 0.0 0.2 0.4 0.6 50 100 150 200 250

Vbs= 0 V

Id (µA/µm) Vds (V) 0.0 0.2 0.4 0.6 50 100 150 200 250

Vgs-Vt= 0 to 0.8 V at 0.2 V step Lg=70 nm Vbs= -2 V

Id (µA/µm) Vds (V)

Positive Vbs: → Ron ↓ → Id ↑ → Output conductance↓

10

I mpact of Back Bias

• 0.4

0.0 0.4 0.8 100 200 300 400

Vbs=3 V Vbs=0 V Vbs=-2 V

gm (µA/µm) Vgs (V)

Vds=0.5 V Lg=70 nm

• 0.4

0.0 0.4 0.8 10

• 10

10

• 9

10

• 8

10

• 7

10

• 6

10

• 5

10

• 4

Vbs=3 V Vbs=0 V Vbs=-2 V

Id (A/µm) Vgs (V)

Vds=0.05 and 0.5 V Lg=70 nm

Positive Vbs: → Vt ↓ → gm ↑ → S ↑ → DIBL ↓

11

Vbs decreases Vbs decreases

I mpact of Back Bias on Vt and Rsd

• Rsd modulation
• Vt tunability: ∆Vt= 200 mV for ∆Vbs= =±4 V

12

• 4
• 2

2 4 600 800 1000 1200

Rsd (Ω.µm) Vbs (V)

• 150
• 100
• 50

50 100

Vt,sat (mV) [Lg=1 µm]

I mpact of Back Bias

• n Subthreshold Swing

Positive Vbs → S ↑

• 2
• 1

1 2 3 125 150 175 200 Lg=70 nm Vds=0.5 V Smin (mV/dec) Vbs (V)

Positive Vbs → Deeper electron centroid in channel Poisson-Schrödinger simulation

• 4

4 8 12 16

• 1

1

y (nm) Ec (eV)

HfO2 Channel Buffer

• 4

4 8 12 16 2 4 6 8 10 x 10

18

y (nm) n (cm-3) Vbs= - 2 V Vbs= 2 V Vbs= 0 V

(a) (b)

Ns=4x1012 cm-2 Vbs=-2V 2V

I mpact of Back Bias

• n DI BL

Positive Vbs → DIBL ↓

• 2
• 1

1 2 3 70 80 90 100 110 120 130 Lg=70 nm Vds=0.5 V DIBL (mV/V) Vbs (V)

Positive Vbs → Si space charge region shrinks → Ground plane moves closer to channel TCAD simulation of space charge

14

p-Si S D BOX

Space charge (cm-3) 1x1018

• 1x1018

Vds=0.5 V Vgs-Vt=0.1 V Vbs=0

depletion region G 100 nm

• Low frequency dispersion, CET~ 2 nm
• Lower mobility for negative Vbs

→ Confinement increases

• Front gate leakage < 10-3 A/cm2 at Vg=1 V

CV and Mobility

• 0.5

0.0 0.5 1.0 0.0 0.5 1.0 1.5 2.0

Lg = 1 µm

C (µF/cm

2)

Vgs (V)

1 - 100 kHz

2 4 6 8 500 1000 1500 2000 2500

Vbs=-3 V

µ

e (cm 2/Vs)

Ns (x10

12cm

• 2)

Vbs=0 V Vbs=3 V

15

Benchmarking of S, DI BL and Mobility

• Excellent S, DIBL and

transport properties

This work (Vbs= 0 V) IEDM13 Kim VLSI13 Irisawa VLSI13 Kim[T50] IEDM12 Czornomaz

5 10 15 20 50 500 1000 1500 2000

Ns=7x10

12 cm

• 2

µ

e (cm 2/Vs)

tch (nm)

0.1 1 100 200 300

Planar III-V-O-I MOSFETs This work (Vbs=0) VLSI13 Kim VLSI12 Kim (InAs) IEDM12 Czornomaz IEDM13 Czornomaz

DIBL (mV/V) Lg (µm) 0.1 1 100 150 200

Vds=0.5 V

This work (Vbs=0 V) VLSI13 Kim VLSI12 Kim (InAs) IEDM12 Czornomaz APL11 Takei (InAs)

Smin (mV/dec) Lg (µm)

Planar III-V-O-I MOSFETs

16

Conclusions

• Demonstrated self-aligned In0.7Ga0.3As MOSFETs
• n III-V-O-I on p-type silicon substrate
• Promising performance, need to lower Rsd
• Back gate bias allows wide tunability of device

characteristics

17