Lecture 17: Scheduling Sanjay Rajopadhye Computer Science, Colorado - - PowerPoint PPT Presentation

High-Performance Embedded Systems-on-a-Chip

Lecture 17: Scheduling

Sanjay Rajopadhye Computer Science, Colorado State University

High-Performance Embedded Systems-on-a-Chip – p.1/18

Limitations of Systolic Arrays

Only a (very small) proper subset of SAREs: Those that

• are Serializable,
• are Localizable,
• correspnod to a Single Equation, and
• admit a One-dimensional schedule.

Question: What is beyond systolic arrays?

High-Performance Embedded Systems-on-a-Chip – p.2/18

(Silicon) Compilation

• For each point in domain of each variable,

determine:

• A time instant

schedule

• A place

processor and memory allocation

• Transform P-SARE so that indices denote either
• time,
• processor, or
• memory address
• Generate code (or HDL, we hope)

High-Performance Embedded Systems-on-a-Chip – p.3/18

Two Orthogonal Issues

• Static Analysis: what transformation to apply
• scheduling
• processor (& memory) allocation
• Program Transformation: manipulating the SARE
• Rules to modify the SARE (Change of Basis)
• Code Generation (how to interpret the

transformed SARE)

High-Performance Embedded Systems-on-a-Chip – p.4/18

Golden Rule of Static Analysis

The dependence graph cannot be explicitly constructed

• Too large
• Not (fully) known at compile time – parameters
• Explicitly constructed results are not useful

Implication: use compact information

High-Performance Embedded Systems-on-a-Chip – p.5/18

Compact information

Reduced Dependence (Multi) Graph (RDG)

• Nodes

variables in the SARE

• Edges

for each occurrence of

• n the rhs
• f the equation for

edge from

to

. Labeled with

• the dependence function,

• the (sub) domain of

where it occurs

• Miscellaneous info (eg. duration, etc.)

High-Performance Embedded Systems-on-a-Chip – p.6/18

Key Problem: Scheduling

• Definition: A function

such that whenever

depends on

, then

.

• Affine schedules:

Geometric interpretation: all points executed at time

belong to isotemporal hyperplane with normal vector

High-Performance Embedded Systems-on-a-Chip – p.7/18

Scheduling a (single) URE

Its RDG is just

• ne node,
• with

self loops,

• each labeled with a vector

.

High-Performance Embedded Systems-on-a-Chip – p.8/18

Scheduling a single URE

• ✻

is valid iff for

, and

i.e.,

• Finite number of constraints, independent of

domain size. Scheduling

Linear Programming

• Geometric view: Choose the hyperplanes so that

dependences point backwards

High-Performance Embedded Systems-on-a-Chip – p.9/18

Example

• ❇❍

Schedule validity conditions

i.e.,

Optimal schedule:

High-Performance Embedded Systems-on-a-Chip – p.10/18

Scheduling an SURE

• Single schedule for all variables

Not general enough: some well defined SURE’s don’t admit such a schedule (e.g. the convolution example)

• Shifted linear schedules

Allow the

to be different for each variable,

, but same

also not general enough

• Variable dependent schedules: different slopes for

different variables) not general enogh either

• Multidimensional schedules most general, but still

not enough

High-Performance Embedded Systems-on-a-Chip – p.11/18

Limits of shifted linear schedules

• This SURE cannot be scheduled with same-slope

lines for both

and

.

• But do a simple CoB—transpose one of the

vars—and now it can.

High-Performance Embedded Systems-on-a-Chip – p.12/18

A less contrived example

Optimal solution

High-Performance Embedded Systems-on-a-Chip – p.13/18

Variable dependent schedules

High-Performance Embedded Systems-on-a-Chip – p.14/18

Exercise

• ✂

Find length of longest path reaching the green (cf. red) node at

High-Performance Embedded Systems-on-a-Chip – p.15/18

Solution

• The SURE is inherently sequential (exercise: check it)

• Schedule is quadratic NOT AFFINE
• Generalization: polynomial schedules
• Break down of geometric interpretation as hyperplanes

High-Performance Embedded Systems-on-a-Chip – p.16/18

Polynomial/Multidimensional Schedules

High-Performance Embedded Systems-on-a-Chip – p.17/18

Scheduling Algorithm

• ✻

is valid iff for

, and

i.e.,

• Finite number of constraints, independent of

domain size. Scheduling

Linear Programming Geometric view: Choose the hyperplanes so that dependences point backwards

High-Performance Embedded Systems-on-a-Chip – p.18/18