New FETs [Spectrum 11/2011, 01/2013 and 08/2019] The smaller you - - PowerPoint PPT Presentation

New FETs

[Spectrum 11/2011, 01/2013 and 08/2019]

The smaller you make a CMOS transistor, the more current it leaks

• between gate and channel
• silicon oxide insulator replaced with hafnium oxide,

reducing the tunneling of electrons

• between source and drain when it’s switched off (small

distance between source and drain -> poor gate control)

• thin silicon channel turned by 90 degrees, creating a

“fin”

• - gate brackets the channel on three sides

• Cadence has already spent some 4000 man-years
• verhauling computer code for today’s generation of chips

so that processor operation can be simulated in a realistic time frame

• It will cost the foundries and their partners some US $6

billion to develop the manufacturing process and the computational tools needed to make14-nm and 16-nm chips

[Spectrum, Aug 2019]

• Right now, 7 nm is the cutting edge
• Samsung and TSMC are moving to the next node, 5 nm
• following node: 3 nm
• limited manufacture around 2020
• completely new design

FinFET’s shortcomings 1. more width -> more current -> faster switch

• the transistor fins can’t vary very much in height without

interfering with the interconnect layers

• 2. gate surrounds the fin on only three sides -> some

leakage current when the transistor is off

Evolution of the FET

Gate-all-around, or stacked nanosheet FET

Sacrificial layers, selective chemical etchants, and advanced atomically precise deposition technology are needed to make nanosheets

And then?

• To a large degree, what’s at issue here is heat
• power density limited to about 100 watts per cm2
• more energy-efficient transistors are needed
• Potential solution: new materials for the channel
• faster electrons -> lower VDD
• Ge, GaAs, InGaAs
• n-type InAs and p-type GaSb (gallium antimonide)
• SiGe (because Ge still has some manufacturing

process and reliability issues)