Compact Modelling Techniques in Thin Film SOI MOSFETs Benjamin - - PowerPoint PPT Presentation
Compact Modelling Techniques in Thin Film SOI MOSFETs Benjamin Iiguez Denis Flandre* Departament dEnginyeria Electrnica, Elctrica i Automtica ETSE; Universitat Rovira i Virgili Avinguda dels Pasos Catalans, 26 43007 Tarragona
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Departament d’Enginyeria Electrònica, Elèctrica i Automàtica ETSE; Universitat Rovira i Virgili
Avinguda dels Països Catalans, 26 43007 Tarragona (Spain) E-mail: benjamin.iniguez@urv.cat
*Microelectronics Laboratory, Universite catholique de Louvain (UCL) Louvain-la-Neuve (Belgium)
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MOSFET scaling trend in near future will not be as straightforward as it has been in the past because fundamental material and process limits are imminent. In order to reach below the 32 nm technology node, implementation of advanced, non-classical MOSFETs with enhanced drive current and acceptable control of short channel effects are needed. Advanced thin-film SOI MOSFETs (e.g., single or multiple-gate MOSFETs) are very promising structures for the downscaling of MOSFETs below the 32 nm technological node.
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Higher saturation current
Smaller mobility degradation
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The non-classical multi-gate devices such as Double-Gate (DG) MOSFETs, FinFETs or Gate-All-Around (GAA) MOSFETs show an even stronger control of short channel effects, and increase of on- currents taking advantage of volume inversion/accumulation.
DG MOSFET
GAA MOSFET FinFET
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Current Total charges Transconductance and conductance Transcapacitances
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The good electrostatic control of the channel by the gate in ultrathin body MOSFETs (full depletion in subthreshold, i.e., no punchtrough) allows to use undoped or lightly-doped Si bodies. Mobility is higher in undoped bodies than in doped ones. In ultrathin body MOSFETs, a proper description of the electrostatics should take into account the effects of both dopants and charge carriers. In FD SOI MOSFETs the Si film is fully depleted, while the front and back interface can be inverted, depleted or accumulated
In Multi-Gate MOSFETs, the Si body can be fully inverted or accumulated (volume inversion or accumulation)
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Generally, in single or double-gate SOI MOSFETs the electrostatic potential in the semiconductor body, φ(x,y), is given by Poisson’s equation: where x and y are the direction parallel and perpendicular to the gate, respectively, and Na is the acceptor doping density in the silicon body (n- channel device), n is the electron density and εSi is the dielectric permittivity of silicon.
( )
n N q y x
a si
+ = ∇ ε ϕ ) , (
2
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If we consider that the device is in quasi-equilibrium (which is consistent with the drift-diffusion transport mechanism), and we neglect quantum confinement, the electron density becomes:
Here, is the intrinsic carrier density in silicon, VT is the thermal voltage, and is the non-equilibrium quasi-Fermi level referenced to the Fermi level in the
source bias. The corresponding boundary conditions for φ are:
T F
V a i e
N n n
/ ) ( 2 φ ϕ −
=
T F
V ie
n n
/ ) ( φ ϕ −
=
i
n
F
φ ) , ( = y
F
φ
DS F
V y L = ) , ( φ
bi
V y = ) , ( ϕ
DS bi
V V y L + = ) , ( ϕ
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In addition, the boundary conditions for at a given silicon-insulator interface is: where Coxi = εox/toxi is the gate insulator capacitance per unit area, εox and toxi are the insulator permittivity and thickness, respectively, tSi is the silicon body thickness, VGS is the gate-source voltage, φMS is the gate work function referenced to the silicon body, Vbi is the built-in voltage between the body and the source or drain contacts, and Qi is the total charge sheet density (per unit area of the gate) controlled by the vertical field at the i-interface . The above equation arises from the continuity of the normal component of the displacement vector across interfaces.
i t y Si i MS GS
Q y y x t x V C
i
≡ ∂ ∂ = − −
=
) , ( )) , ( ( ϕ ε ϕ φ
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= ∂ ∂
= y
y ϕ
= ∂ ∂
= r
r ϕ
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The first step to develop a compact model is to consider a well behaved device, with good electrostatic control by the vertical field (from the gate) and where the derivative of the lateral field in the direction of the channel length can be neglected compared to the derivative of the vertical field in the direction perpendicular to the channel. This is the gradual channel approximation, and simplifies the electrostatic analysis. This leads to neglect the short-channel effects In thin-film SOI MOSFETs, we expect that a long-channel device model can be applied to significantly shorter channels than in standard MOSFETs We also have considered an n-channel device, with acceptor doping or with no
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In a doped thin-film SOI MOSFET: The surface electric field can be written in terms of the mobile charge density (in absolute value) per unit area at each interface, Q, and the depletion charge density per unit area (in absolute value) QDep=qNAtSi (tSi being the Si film thickness) whatever x:
( ) ( ) [ ]
( ) [ ]
+ = + =
− ) ( , 2 2 2
, ,
x V y x kT q A i A Si A Si
e N n N q y x n N q dy y x d
φ
ε ε φ
( )
Si Dep S
Q x Q x E ε 2 ) ( + =
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is possible with the following assumptions:
thickness of the depleted region, i.e., the Si film)
the front channel may occupy a non-negligible portion of the Si thickness
( )
− + − − − − = ) ( 2 2 x C Q V V C C C Q V V C x Q
s
d fbb GB
bb
d fb GF
αϕ
b
b
bb
C C C C C + =
( )
b
b
C C C C C + + =1 α
Si Si b
t C ε =
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No need to linearize the charge in FD SOI MOSFETs to obtain a relatively simple model Charge-based and surface-potential based models are equivalent Expressions of total charges can be derived from this linear relationship
)
− + − =
d s d s DS
C Q Q Q Q q kT L W I α µ 2
2 2
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If the doping is high, and the mobile charge can be neglected in the subthreshold regime, a simple solution for the potential can be obtained, which leads to an analytical expression of the threshold voltage that includes the scaling dependences (and therefore the threshold voltage roll-off and DIBL):
is the solution of the 1D Poisson’s equation, which includes the doping charge term, and is the solution of the remaining 2D Laplace equation. Additional approximations are needed to solve the 2D Laplace’s equation
) , ( ) ( ) , (
2 1
y x y y x ϕ ϕ ϕ + =
) (
1 y
ϕ ) , (
2
y x ϕ
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In FD SOI MOSFETs the 2D Poisson’s equation in subthreshold can by solved by neglecting the mobile charge density, which is much lower than the doped charge density An analytical expression of the threshold voltage, that takes into account the scaling dependencies, the roll-off and the DIBL can be obtained from that solution after using several approximations and a few adjustable parameters (quasi-2D model). The electrostatic short-channel effects are accounted for (in many models) by means of the threshold voltage expression, which is used in the drain current expression derived for long-channel devices Standard FD SOI MOSFET models take into account the short-channel effects using this approach
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Developed as an extension of a bulk MOSFET model It extends a strong inversion explicit model by using proper interpolation functions It includes a smooth transition between the PD and the FD regime (Dynamically Depleted SOI MOSFET) Temperature dependence of threshold voltage, mobility, saturation velocity, parasitic resistance, and diode currents Different gate resistance options for RF simulation:
rapid transientMOSFET operations
Last version: BSIMSOI 4.0: addresses several new issues in modeling sub-0.13 micron CMOS/SOI high-speed and RF circuit simulation.
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magnitude of the noise density
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and one model for FD SOI MOSFETS (FD/SOI UFSOI)
and underlying BOX for subthreshold-region operation.
accumulation region where it accounts for the majority-carrier charge, and hence dynamic floating-body effects.
Two dimensional analysis for weak-inversion current Spline interpolations of current and charge across a physically defined, bias-dependent moderate-inversion region linking the weak- and strong- inversion formalisms
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Temperature dependence is also implemented, without the need for any additional parameters Physics-based noise modeling for AC simulation, which accounts for thermal noise from the channel and parasitic series rresistances, shot noise at the source and drain junctions, and flicker noise in the channel. The temperature-dependence modeling is the basis for a self-heating
node. Because of the process basis of the models, parameter evaluation can be based in part on device structure Option for a strained Si/SiGe channel.
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Based on a complete surface-potential description. The surface potential in the MOSFET channel, and the potentials at both surfaces of the buried oxide This allows to include all relevant device features of the SOI-MOSFET An additional parasitic electric field, induced by the surface-potential distribution at the buried oxide, has to be included for accurate modeling
It seems to have better convergence properties than BSIMSOI and UFSOI It includes a 1/f noise model
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pMOS devices can be AM SOI MOSFETs
subthreshold (full depletion), above threshold conduction in the quasi- neutral region, and surface accumulation
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dependent depletion region width, changing along the channel, must be considered, as well as an equation relating the accumulation charge sheet density with the surface potential.
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No models currently available in circuit simulators. They face important challenges for nanoscale devices: scaling with volume inversion/accumulation, quantum confinement, hydrodinamic transport Models under development:
BSIM-MG (based on BSIMSOI) UFDG (extension of FD/SOU UFSOI)
Applicable to symmetrical DG, assymmetrical DG MOSFETs, UTB
SOI MOSFETs and FinFETs
It considers quantum confinement self consistently (Compact Poisson-
Schrödinger Solver)
It accounts for velocity overshoot The carrier transport and channel current are modeled as quasi-ballistic
via an accounting for velocity overshoot, derived from the Boltzmann transport equation and its moments, and a QM-based characterization of mobility
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By integrating the Poisson’s equation between the centre (y=0) and the top surface of the film (y=-tsi/2) we get: where is the surface potential and is the potential in the middle of the film. Unfortunately, the potential at the center is unknown and we cannot analytically integrated for the potential. An analytical model is possible with an approximate expression of the difference between the two potentials:
threshold [Francis 94, Moldovan 07]; this is valid up to well above threshold.
( ) ( )
( ) [ ] ( )
− + − =
− − −
1 2
2 2 φ φ φ
φ φ ε
s S
kT q x V kT q A i s Si A S
e e N n q kT qN x E
( )
2 / ,
Si S
t x − = φ φ
( )
, x
φ =
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For undoped DG MOSFETs, Poisson’s equation is: By solving Poisson’s equation with the appropriate boundary conditions [Taur 04]:
The following relation is obtained:
electrode and the intrinsic silicon
− =
Si Si i Si
t x kT n q t β ε β 2 cos 2 2 log q 2kT V ψ(r)
2
( )
( )
kT V x q i Si
e n q dx V x d dx x d
−
⋅ ⋅ = − =
) ( 2 2 2 2
) ( ) (
ψ
ε ψ ψ ( ) ( ) ( ) [ ] ( )
β β ε ε β β ε ϕ tan 2 cos log log 2 2 log 2
2 Si
Si i Si Si GS
t t n q kT t kT V V q + − = − − ∆ −
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The drain current is obtained as:
( )
∫
=
DS
V DS
dV V Q L W I µ
( )
β β ε tan 2 2 2 dy dψ ε 2 Q
2 / t y Si
Si
Si Si
t q kT = =
=
( ) ( )
s d
Si
Si Si Si
t t q kT t L W
β β
β β ε ε β β β ε + − =
2 2 2 2 D
tan 2 tan 2 4 I
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where CSi is the silicon capacitance and Cox is the oxide
capacitance.
+ + + = − + ∆ − q kT C Q C C q kT C Q q kT C Q C C q kT q kT C t qn q kT Vgs
Si
Si
Si i
8 log 8 log 2 log 8 log ) V
ϕ
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( )
∫
=
DS
V DS
dV V Q L W I µ
+ + − − = 2 2 Q Q dQ Q dQ q kT C dQ dV
( )
+ + + − + − =
2 2 2
2 2 log 8 4 2 Q Q Q Q C q kT C Q Q Q Q q kT L W I
s d Si
d s d s DS
µ
Si
C q kT Q 4
0 =
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In a well-behaved cylindrical GAA MOSFET, the electrostatic behaviour
direction. In an undoped cylindrical n-type SGT-MOSFET Poisson’s equation takes the following form (in cylindrical coordinates): where , ψ(r) the electrostatic potential and V the electron quasi- Fermi potential. Boundary conditions:
Exact solution: B determined from boundary conditions
( )
kT V q
e q kT dr d r dr d
−
⋅ = +
ψ
δ ψ ψ 1
2 2
Si i
kT n q ε δ /
2
=
s
R r r dr d ψ = = ψ = = ψ ) ( , ) (
+ − + =
2 2 )
Br δ(1 8B q kT V ψ(r) log
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From Gauss law: Using ,the charge control model that is obtained is: where The drain current is calculated from: Using we obtain:
) 4 (
R r Si s GS
dr dψ ε Q ) ψ
C
=
= = − ϕ −
2
1 4 BR BR q kT dr dψ
R r
+ − =
=
( )
+ + + = − − ϕ −
2 GS
Q Q Q q kT Q Q q kT C Q δR 8 q kT V
log log log
q kT R 4ε Q
Si 0 =
∫
=
DS
V DS
Q(V)dV L R 2π
( )
+ + + − + − µ π =
2 2
log 2 2 2 Q Q Q Q Q q kT C Q Q Q Q q kT L R I
s d
d s d s ds
+ + + − =
Q Q dQ Q dQ q kT C dQ dV
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Transfer characteristics, for VDS=0.05V (a) and for VDS=1V (b) in linear scale and in logarithmic scale Solid line: Atlas simulation; Symbol line: our compact model doping level NA=6.1017 cm-3; silicon thickness tSi=31nm; oxide thickness tox=2nm; channel length L=1µm and width W=1µm.
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Output and transfer characteristics obtained from the analytical model (solid lines) compared with numerical simulations from DESSIS-ISE (symbols).
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( )
+ + + = − − −
GS
Q Q Q log q kT Q Q log q kT C Q V V V
Charge associated to top, lateral and total charge calculated with ATLAS 3-D simulations and with the unified charge control model (FinFET with Wfin=10 nm, Hfin=50 nm)
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( )
( )
2 2 1 1 2 2
4 1 1 1 log 1 1 1 1 2 1 2 log log(2 ) log log 1 1 1
Si GS GB fb fb GS GB fb fb
C V V v v kT V V V v v kT q C q kT kT Q kT Q kT Q a q q C q Q q Q α α α α α α α α α − + − + − − − − ⋅ − + + + + − − + = + + + + +
Si Si
C C C α = +
Si Si
C t ε =
( )
2 1
4
Si GS fb fb
Q C V v v = + −
Si
D
t a L ε ε =
2 Si D i
kT L q n ε =
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0.5 1 1.5 2 1 2 3 4 x 10
IDS [A] VGS [V]
(a) (b)
0.5 1 1.5 2 10
10
10
10
10
10
10
IDS [A] VGS [V]
(a) (b)
channel length L=1µm, width W=1 µm, silicon oxide thickness tox=2 nm and silicon film thickness tSi=31 nm .
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If the doping is high, and the mobile charge can be neglected in the subthreshold regime, a simple solution for the potential can be obtained, which leads to an analytical expression of the threshold voltage that includes the scaling dependences (and therefore the threshold voltage roll-off and DIBL):
the solution of the 1D Poisson’s equation, which includes the doping charge term, and is the solution of the remaining 2D Laplace equation. In GAA MOSFETs, the solution is written as: Additional approximations are needed to solve the 2D Laplace’s equation
) , ( ) ( ) , (
2 1
y x y y x ϕ ϕ ϕ + =
) (
1 y
ϕ ) , (
2
y x ϕ ) , ( ) ( ) , (
2 1
r x r r x ϕ ϕ ϕ + =
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dependencies, the roll-off and the DIBL can be obtained from that solution after using several approximations and a few adjustable parameters (quasi-2D model). The electrostatic short-channel effects are accounted for (in many models) by means of the threshold voltage expression, which is used in the drain current expression
functions (GAA MOSFETs)
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Subthreshold swing for DG MOSFET with tox=2nm. VDS=10 mV.
) 10 ln( 1 ⋅ − =
gs t
S V Swing
[ ] ∫
=
min
/ ,
2
t V y x i inv
dy e n Q
T
φ
The threshold voltage is defined as the value of the gate voltage to obtain a certain value of the mobile sheet charge density at the position of the potential minimum (virtual cathode)
− ⋅ ⋅ − + = ds S t i n TH Q T V gs S ms TH V
ln 1 1 φ
⋅ + =
i n TH Q T V ms TH V 2 ln φ
For Long Channel DG MOSFET
Subthreshold Swing Threshold Voltage Model
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ds S gs S t i n TH Q T V TH V
− − ⋅ = ∆ 1 1 1 2 ln
− − − − − − − ⋅ = gso S S gso S S gs S gso S t i n TH Q T V DIBL
ds dso
1 1 1 1 1 2 ln
Threshold Voltage Roll-off, and DIBL Models
Sgso and Sdso are the values of Sgs and Sds at low VDS
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Schematic view of the DG MOSFET cross-section (a). The extended body maps into the upper half-plane of the (u, iv) plane (b), where the u-axis, the iv-axis, and the bold semicircle with radius 1/√k represent the boundary, the G-G and the S-D symmetry axis, respectively. The four corners of the boundary are located at u = ±1 and ±1/k.
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2D/3D potential model in subthreshold derived using conformal mapping 1D potential model well above threshold (kernel model) 4th order polynomial expression of the potential in the transition regime, imposing continuity everywhere
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x y ∆L S D G G L tsi GCA region Saturation region
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( )
si e 2 2 2 2
, q
φ φ y x n y x − = ∂ ∂ + ∂ ∂
( ) ( ) ( )
n
y x c y x b a y x + + = , φ
2 /
=
=tsi y
dy dφ
gs S
y si
t V dy d ϕ φ ε φ ε ∆ + − =
=0
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( )
n n si
FB gs S si
FB gs S si
S
y t t n V V y t V V y x
1
2 ,
−
⋅ + − − + − + = φ ε ε φ ε ε φ φ
for
2
si
t y ≤
( ) ( ) ( )
n si n si
gs S si
si
gs S si
S
y t t t n V y t t V y x − ⋅ ∆ + − − − ∆ + − + =
−1
2 , ϕ φ ε ε ϕ φ ε ε φ φ
for
2
si
t y >
FB gs S si
si m tsi
t V V Q dy x + − + − = ∂ ∂
∫
φ ε ε ε φ 2
2 2
Qm is considered constant in the saturated region
2 2 2
= − ∂ ∂ λ ϕ ϕ x
m gs S
C Q V 2 − ∆ + − = ϕ φ ϕ
( ) ( )
1 1 2 1 2 1 2 1 2 1 8 2
2
+ − + = + − + = n n r t n n t t t
si si
si
si
ε ε λ
We have to solve in the x-direction:
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( )
( )
sat b deff S
V L x ϕ φ φ ϕ ϕ = + = = ∆ − = µ ϕ
sat L x
v k dx d =
∆ − =
∆L, vsat, Vdeff being respectively the length of the saturation region, the saturation velocity, and the effective drain-source voltage. φb is the surface potential at the source and at threshold condition k=2 for nMOSFETs. k=1 for pMOSFETs
+ ∆ + + ∆ = λ λ µ λ ϕ ϕ x L v k x L x
sat sat
sinh cosh ) (
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( ) ( )
b ds S d
V x φ φ ϕ ϕ ϕ + = = = =
+ + − + = ∆ λ µ ϕ λ µ ϕ ϕ ϕ λ
sat sat sat sat d d
v k v k L
2 2 2
ln
m
m s deff
m t gs deff sat
C Q C Q Q V C Q V V V 2 4 2 − + + ≈ − + − = ϕ
m
m s ds
m t gs ds d
C Q C Q Q V C Q V V V 2 4 2 − + + ≈ − + − = ϕ
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1 2 10 20 30 40
(a)
L=50nm tox=2nm tsi=15nm tsi=30nm
Vgs-Vt
∆L (nm)
Vds (V)
Vgs-Vt=0.25 and 0.5V. L = 50nm
0.0 0.5 1.0 1.5 2.0 10
10
10
10
10
(c) Vg
Symbols = Silvaco Lines = Model Vg = 0.4V, 0.75V, 1V, 1.5V
Gd (A.V
Vds (V)
Comparison of the model with Silvaco simulations, for a DG-MOSFET with tox=2nm, tsi=15nm and L=50nm.
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Where φ2D(y,z) is the 2D potential and related to 1D potential as With boundary conditions VGS1 is the potential applied on both left/right and top gate and VGS2 is the
potential applied on the bottom gate
) , , ( ) , ( ) , , (
3 2
z y x z y z y x
D D
φ φ φ + =
2 1 1 2
) ( ) ( ) ( ) , ( z y z y y z y
D
⋅ + ⋅ + = α α φ φ
[ ]
) , ( ) , (
2 2 1 1 h z D Si
ms GS
z z y h z y V C
=
∂ ∂ − = = − − ⋅ φ ε φ φ
[ ]
) , ( ) , (
2 2 2 2 h z D Si
ms GS
z z y h z y V C
=
∂ ∂ = − = − − ⋅ φ ε φ φ
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t
V y i si
e n q y y
/ ) ( 2 2
) (
φ
ε φ = ∂ ∂ ) (
1
= ∂ ∂
= y D
y y φ
[ ]
y si
ms GS
y t y V C
=
∂ ∂ ⋅ − = = − − ⋅
1 1
) ( φ ε φ φ
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The 3D potential component is the solution of the remaining 3D Laplace’s equation with boundary conditions An analytical expression is found for φ3D The approximations used to obtain the analytical solution were to consider that:
to its value at the source end of the channel
the short-channel effects are not very severe, so that φ1D is the dominant
potential contribution for the electron charge density
[ ]
) , , ( ) , , (
3 3 1 h z D Si
z z y x h z y x C
=
∂ ∂ − = = − ⋅ φ ε φ
[ ]
) , , ( ) , (
3 2 2 h z D Si
z z y x h z y C
=
∂ ∂ = − = − ⋅ φ ε φ
) , ( ) , , (
2 3
z y V z y
D bi D
φ φ − = ) , ( ) , , (
2 3
z y V V z y L
D bi DS D
φ φ − + =
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analytical expression of the location of the virtual cathode (the point along the channel where the potential is minimum, and therefore, of the minimum value φmin
subthreshold swing and threshold voltage expressions.
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If the silicon layer in the DG and GAA MOSFETs is thinner than 10 nm, quantum confinement cannot be ignored, and Poisson’s equation should be solved self-consistently with Schrödinger’s equation. For this case, an analytical solution is not possible without making assumptions
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effective oxide capacitance that takes into account the position of the inversion centroid, which is a function of the inversion charge:
*
1
I
si
C C y C ε = + 1 1 1 ·
n I I si I I
N y a b t y N = + +
0.5 1 1.5 2 0.01 0.02 0.03 0.04 Gate Voltage V
gs (V)
Inversion Charge Q (F/m
2)
tsi =5 nm N
A=1017 cm-3 Numerical Quantum Numerical Classical Infinite Quantum Well Quantum Compact Model Classical Compact Model Expression (18)
0.5 1 1.5 2 0.01 0.02 0.03 0.04 0.05 Gate Voltage V
gs (V)
Inversion Charge Q (F/m
2)
tsi =10 nm N
A=1017 cm-3 Numerical Quantum Numerical Classical Infinite Quantum Well Quantum Compact Model Classical Compact Model Expression (18)
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charge control model (solid-line) for a FinFET with (Wfin=10 nm, Hfin=30 nm, tox=1.5 nm, tbox=50 nm).
0.5 1 1.5 2 2.5 2 4 6 x 10
Vg (V) Q (C/m
2)
0.5 1 1.5 2 2.5 10
10
10
10
Vg (V) Q (C/m
2)
∇ ∇
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In extremely short channel DG MOSFET the channel is quasi-ballistic, thus an important overshoot velocity is expected Using a simplified energy-balance model, the electron mobility is a function of the electron temperature related to the average energy of the carriers.
( ) 2
e e x w
dT T T q E x dx k λ − + = −
w sat w
v τ λ 2 ≈
τw: energy relaxation time
( ) ( ) ( ) 2 2
w
y x e w
q q T x T V x V e d k k
ξ λ
ξ ξ λ
−
= + −
Using Ex(x)=-dV(x)/dx
MOS-AK September 2008 B. Iñiguez 65
In contrast with classical drift-diffusion models, the saturated velocity in the saturation region due to non-stationary effects can achieve several times the stationary saturation velocity, vsat. This phenomenon is known as velocity overshoot. In linear region, the carrier velocity can be obtained from the mobility:
( ) ( ) ( ) ( ) 1 ( ( ) )
n n x x e
v x x E x E x T x T µ µ α = = + −
2
n w sat
k q v µ α λ =
( )
, ( ) ( ) ( )
( ) 1 1
si eff
n si eff ph bulk ph bulk ph t sr
U t E U UO µ µ θ µ µ µ = + − + 4
dep eff Si
Q Q E ε + ≈
MOS-AK September 2008 B. Iñiguez 66
Using the charge control models previously presented and the velocity expression given above, the drain current in the linear channel region can be
As a first approximation, in the linear region we can suppose that the lateral field is linear from a small value at the source end to the saturation field at x=Le (Ex=Esat·x/Le).
( ) ( )
( ) ( ) 1 ( ( ) ) 1 ( ( ) )
Dsat Dsat e e
V V n eff DS L L e e
W Q V dV W Q V dV I T x T dx T x T dx µ µ α α = = + − + −
∫ ∫ ∫ ∫
( , ) ( , ) 1 ( ) 2
e e w
eff gs DSS eff gs DSS DS L L e n DSS e
W f V V f V V W I L V q L V e d k
ξ λ
µ µ γ α ξ ξ
−
= = + +
( )
e w e sat eff n
L L v λ µ γ 2 1 1 + =
VDSS: effective drain-source voltage
MOS-AK September 2008 B. Iñiguez 67
Drain Current (mA/µm)
Temperature Model: Quantum Classical
0.5 1 1.5 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 Drain Voltage (V) Drain Current (mA/µm) 0.5 1 1.5 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 Drain Voltage (V)
Drift-Diffusion: Quantum Classical
A comparison of drain current for FinFET (Wfin=10 nm, Hfin=30 nm, tox=1.5 nm, tbox=50 nm)), L=100 nm, for classical charge control (•) and quantum charge (-) using a) Temperature model b) Drift-Diffusion model. The gate voltages are Vgs-VTH=0.5, 0.75, 1 and 1.25 V.
MOS-AK September 2008 B. Iñiguez 68
The total channel charge is obtained by integrating the mobile charge density
In doped DG MOSFETs, using the charge control model above explained: The total gate charge is: QG=-QTot-Qox+WLQDep, where Qox is the total oxide fixed charge at both front and back interfaces.
( )
∫ ∫
− = − =
L V DS Tot
DS
dV Q I W Qdx W Q
2 2
2 2 µ
( )
∫
+ + + − =
d s
Q Q Dep
DS Tot
dQ Q Q Q q kT Q q kT C Q I W Q
2 2 2
2 µ
( )
[ ]
d s
Q Q Dep Dep Dep
DS Tot
Q Q Q Q Q Q q kT Q q kT C Q I w Q + + + − + + − = log 2 2 3 2
2 2 2 3 2
µ
MOS-AK September 2008 B. Iñiguez 69
The total drain and source charges are obtained as: The transcapacitances are necessary to develop the small-signal model. They are obtained by differentiating the total charges with respect to the applied voltages. There are 6 transcapacitances. 4 of them are independent.
( ) ( )
dQ Q Q Q q kT C Q Q Q Q Q Q Q q kT C Q Q Q LI w Qdx L x W Q
Dep
Q Q Dep s Dep Dep s
s DS L D
d s
+ + + ⋅ ⋅ + + − − + − = − =
∫ ∫
1 1 1 log 2 2 2 2
2 2 2 2 2 3
µ
D Tot S
Q Q Q − =
MOS-AK September 2008 B. Iñiguez 70
2 1 1
G F GS
Q W Q V L α α α = + ⋅ + +
2 2 2
2 (1 ) 2
d s
Q Tot DS
Q
Q kT Q Q W Q dQ I C q Q Q µ α = − + + + +
∫
( )
2 2 3 2 2 2
2 1 2 log ( ) 2 (1 ) 2 2 1 1 2 (1 ) 2
d s
Q L s D s DS
s Q
Q Q Q Q x W kT Q W Qdx Q Q Q Q L L I C q Q Q kT dQ C q Q Q Q µ α α − + = = − + − − ⋅ + + ⋅ + + + +
∫ ∫
MOS-AK September 2008 B. Iñiguez 71
The intrinsic capacitances, Cgd and Cgs, are obtained as: where i=d,s The non-reciprocal capacitances Cdg and Csg are obtained as: The capacitances Csd and Cds are computed as follows
dVi dQ C
G gi
− =
ig
C
G i
dV dQ
S D ds
dV dQ C − =
D S sd
dV dQ C − =
MOS-AK September 2008 B. Iñiguez 72
b) and gate to source capacitance (c, d) with respect to the gate voltage, for VDS=1V (a, d) and VDS=0.05V (b,c). Solid line: Atlas simulations; Symbol line: our
Normalized drain to gate capacitance (a, c) and source to gate capacitance (b, d) with respect to the gate voltage, for VDS=1V (a, b) and VDS=0.05V (c,d). Solid line: Atlas simulations; Symbol line: our model. Doped DG MOSFET with NA=6·1017 cm-3
MOS-AK September 2008 B. Iñiguez 73
)
− = − =
L V DS Tot
DS
dV Q I R Qdx R Q
2 2
2 2 µ π π
( )
∫
+ + + − =
d s
Q Q
DS Tot
dQ Q Q Q q kT Q q kT C Q I R Q
2 2 2
2 µ π
( ) ( )
dQ Q Q Q q kT C Q Q Q Q Q Q Q q kT C Q Q Q I L R Qdx L x R Q
Q Q s s
s DS L D
d s
+ + + ⋅ ⋅ + + − − + − = − =
∫ ∫
2 2 2 2 2 3
1 1 1 log 2 2 ) ( 2 2 µ π π
( ) [ ]
d s
Q Q
DS Tot
Q Q Q Q Q Q q kT Q q kT C Q I R Q + + + − + + − =
2 2 2 3 2
log 2 2 3 2 µ π
MOS-AK September 2008 B. Iñiguez 74
Normalized drain to gate capacitance (a, c) and source to gate capacitance (b, d) with respect to the gate voltage, for VDS=1V (a, b) and VDS=0.1V (c, d). Solid line: DESSIS-ISE simulations; Symbol line: analytical model Normalized drain to source capacitance (c,d) and source to drain capacitance (a, b) with respect to the gate voltage, for VDS=1V (a, d) and VDS=0.1V (b, c). Solid line: DESSIS-ISE simulations; Symbol line: analytical model
MOS-AK September 2008 B. Iñiguez 75
∫
− = − =
L V DS Tot
DS
dV Q I W Qdx W Q
2 2
µ
+ + + − =
d s
Q Q
DS Tot
dQ Q Q Q q kT Q q kT C Q I W Q
2 2 2
2 2 µ
( )
dQ Q Q Q q kT C Q Q Q Q Q Q Q q kT C Q Q Q I L W Qdx L x W Q
Q Q s s
s DS L D
d s
+ + + ⋅ ⋅ + + − − + − − = − =
∫ ∫
2 2 2 2 2 3
2 1 1 2 1 2 2 log 2 2 4 ) ( µ
[ ]
d s
Q Q
DS Tot
Q Q Q Q Q Q q kT Q q kT C Q I W Q + + + − + + − =
2 2 2 3 2
2 log 2 4 2 2 6 µ
MOS-AK September 2008 B. Iñiguez 76
Normalized gate to drain capacitance (a, b) and gate to source capacitance (c, d) with respect to the gate voltage, for VDS=0.05V (b,c) and VDS=1V (a,d). Solid line: DESSIS-ISE simulations; Symbol line: analytical model Normalized drain to gate capacitance (a, c) and source to gate capacitance (b, d) with respect to the gate voltage, for VDS=1V (a, b) and VDS=0.05V (c, d). Solid line: DESSIS-ISE simulations; Symbol line: analytical model
0.5 1 1.5 2 0.05 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5
CDG,CSG Normalized Capacitances VGS [V]
(a) (d) (c) (b)
MOS-AK September 2008 B. Iñiguez 77
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 0.1 0.2 0.3 0.4 0.5 0.6 0.7
Normalized Capacitances C
GD,CGS
VGS [V]
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 0.1 0.2 0.3 0.4 0.5 0.6 0.7
Normalized Capacitances C
GD,CGS
VGS [V]
(c) (b) (a) (d)
0.5 1 1.5 2
0.1 0.2 0.3 0.4 0.5 0.6
Normalized Capacitances C
DG,CSG
VGS [V]
(a) (d) (c) (b)
Normalized gate-to-drain capacitance (a, b) and gate-to-source capacitance (c, d) with respect to the gate voltage, for VDS=0.05V (b,c) and VDS=1V (a,d); tsi=31nm. Solid line: analytical model; Symbol line: DESSIS-ISE simulation Normalized drain-to-gate capacitance (a, c) and source-to-gate capacitance (b, d) with respect to the gate voltage, for VDS=1V (a, b) and VDS=0.05V (c, d); tsi=31nm Solid line: analytical model; Symbol line: DESSIS-ISE simulation
MOS-AK September 2008 B. Iñiguez 78
0.5 1 1.5 2 2.5 0.5 1 1.5 2 2.5 3 x 10
Vg (V) C (F/m2)
Gate-to-Channel numerically calculated ( classic and o quantum) and the charge control model (solid-line) for a FinFET with (Wfin=10 nm, Hfin=30 nm, tox=1.5 nm, tbox=50 nm).
∇
MOS-AK September 2008 B. Iñiguez 79
The active line approach, used to extend the model to high frequency operation, is based on splitting the channel into a number of elementary sections Our quasi-static small-signal equivalent circuit, to which we add additional microscopic diffusion and gate shot noise sources, is applied to each section Our charge control model allows to obtain analytical expressions of the local small-signal parameters in each segment
y y+∆y
Cgc
gg ing gc gmVgc in Vg y y+∆y
Cgc
gg ing gc gmVgc in Vg
Cpg Lg Cgs Cgd Ri gm τ Rs Rd Ld Cpd Cds Rds Rs Ls
G D
INTRINSIC S id CORRELATED NOISE SOURCES ig
MOS-AK September 2008 B. Iñiguez 80
The contribution to noise of the length where carriers travel at
A Diffusion Coefficient is used to define the microscopic noise
Mobility reduction should be considered along the channel.
MOS-AK September 2008 B. Iñiguez 81
The active transmission line is analysed using the nodal admittance method Once the intrinsic admittance matrix, Yi, and admittance correlation matrix, CYi, are
Thermal noise is considered for access resistances Gate tunnelling current, and its associated shot noise source are added Using the model, we calculate the S-parameters and the usual noise parameters: Fmin, Rn (equivalent noise resistance) and Gopt (optimum reflection coefficient)
MOS-AK September 2008 B. Iñiguez 82
100 200 300 400 10
1
10
2
10
3
Gate Length (nm) fT (GHz) GAA Vgs-VTH=0.5V DG Vgs-VTH=0.5V DG Vgs-VTH=0.7V SG Vgs-VTH=0.5V 100 200 300 400 10
1
10
2
10
3
Gate Length (nm) fmax (GHz)
GAA 1 finger GAA 10 fingers DG 1 finger DG 10 fingers SG 1 finger SG 10 fingers
MOS-AK September 2008 B. Iñiguez 83
50 100 150 200 10
1
10
2
10
3
Gate Length(nm) fT(GHz) Classical Drift-Diffusion Classical Temperature Model Quantum Drift-Diffusion Quantum Temperature Model
FinFET (Wfin=10 nm, Hfin=30 nm, tox=1.5 nm, tbox=50 nm, Vds=1 V, Vgs-VTH=0.5V).
50 100 150 200 10
1
10
2
10
3
Gate Length(nm) fmax(GHz) Classical Drift-Diffusion Classical Temperature Model Quantum Drift-Diffusion Quantum Temperature Model
MOS-AK September 2008 B. Iñiguez 84
20 40 60 80 100 120 140 160 0.5 1 1.5 2 2.5 3
Gate Length(nm) Fmin(dB) Extrinsic Noise Figure
Classical Drift-Diffusion Classical Temperature Model Quantum Drift-Diffusion Quantum Temperature Model
FinFET (Wfin=10 nm, Hfin=30 nm, tox=1.5 nm, tbox=50 nm, 100 fingers, Vgs-VTH=0.5V, Vds=1V)
20 40 60 80 100 1 2 3 4 5 6 7 Frequency (GHz) Fmin (dB) Classical Drift-Diffusion Classical Temperature Model Quantum Drift-Diffusion Quantum Temperature Model
Extrinsic Intrinsic
MOS-AK September 2008 B. Iñiguez 85
(FD SOI MOSFDETs, AM SOI MOSFETs, DG MOSFETs, GAA MOSFETs, FinFETs)
inversion/accumulation, quantum confinement, hydrodinamic transport
compact analytical way
MOS-AK September 2008 B. Iñiguez 86
We have also reviewed our approaches:
A core model, developed from a unified charge control model obtained from the 1D
Poisson’s equation (using some approximations in the case of DG MOSFETs)
2D or 3D scalable models of the short-channel effects (threshold voltage roll-off, DIBL,
subthreshold swing degradation and channel length modulation), developed by solving the 2D or 3D Poisson’s equation using appropriate techniques
accounts for the position of the inversion centroid
noise analysis