Si CMOS for RF Power Applications J. A. del Alamo MIT Workshop on - PowerPoint PPT Presentation

Si CMOS for RF Power Applications J. A. del Alamo MIT Workshop on Advanced Technologies for Next Generation of RFIC 2005 RFIC Symposium June 12, 2005 Sponsors: DARPA, IBM, SRC

RF power applications

Power vs. frequency GaAs HEMT 50 InP HEMT Si BJT SiGe HBT GaAs / InP HBT 40 GaAs MESFET GaN HEMT Output Power [dBm] LDMOS CMOS 30 20 10 0 0.1 1 10 100 1000 Frequency [GHz] Compilation of research papers from IEEE Xplore by J. Scholvin

Research activity by material and frequency 100 100 SiC above 27 GHz Publications per Year Publications per Year InP 3 to 27 GHz GaN 75 75 below 3 GHz GaAs Silicon 50 50 25 25 0 0 1985 1987 1989 1991 1993 1995 1997 1999 2001 2003 1985 1987 1989 1991 1993 1995 1997 1999 2001 2003 Year Year Compilation of research papers from IEEE Xplore by J. Scholvin

RF power technologies: 1993 vs. 2003 GaAs HBT 12% InP HEMT 12% GaAs HEMT 37% LDMOS 5% 2003 GaAs MESFET 34% InP HBT 3% GaN HEMT SiC InP HEMT 3% 16% Si BJT 3% 1993 LDMOS 3% 5% GaAs HBT Silicon SiGe HBT 16% 34% CMOS 10% 16% GaAs HEMT GaAs MESFET 22% 5% Compilation of research papers from IEEE Xplore by J. Scholvin

RF Power Figures of Merit • PA specs: – Frequency – Power – Gain – Linearity – Voltage PA – Reliability – Power efficiency – Cost

Fundamental trade-off between voltage and frequency scaling

Key to power: supply voltage 100 GaAs & GaN HEMT W f InP HBT 10 Power Density [W/mm] Si BJT 1 GaAs SiGe HBT MESFET HEMT 0.1 CMOS 0.01 LDMOS 0.001 0.0001 0.1 1 10 100 V dd [V] Compilation of research papers from IEEE Xplore by J. Scholvin

Key to frequency: efficiency GaAs/InP HBT 100 InP HEMT GaAs HEMT GaAs MESFET Power Added Efficiency [%] 80 CMOS SiGe HBT LDMOS 60 40 20 0 0.1 1 10 100 1000 Frequency [GHz] Compilation of research papers from IEEE Xplore by J. Scholvin

The benefits of scaling 60 All FETs 27 GHz < f < 50 GHz 40 Peak PAE [%] scaling scaling 20 0 0 0.2 0.4 0.6 0.8 1 L g [µm] Compilation of research papers from IEEE Xplore by J. Scholvin

Gate length scaling in III-V FETs and CMOS 10 Physical Gate Length [µm] 1 0.1 III-V's CMOS CMOS Roadmap 0.01 1970 1980 1990 2000 2010 Year Compilation of research papers from IEEE Xplore Si CMOS: a disruptive technology for RF power? by J. Scholvin

Si MOSFETs for RF power GaAs HEMT 50 InP HEMT Si BJT SiGe HBT GaAs / InP HBT 40 GaAs MESFET GaN HEMT Output Power [dBm] LDMOS CMOS 30 20 10 0 0.1 1 10 100 1000 Frequency [GHz] 1. Extending LDMOS beyond 2 GHz 2. RF power suitability of deeply scaled CMOS

1. Extending LDMOS beyond 2 GHz (PhD Thesis of J. Fiorenza) Source Source LDMOSFET: Lightly-doped Drain MOSFET Drain Drain Gate Gate Source Source Drain Drain Gate Gate n - n - n + n + n + n + n - n - n + n + P P • Two critical sources of RF Loss: – Gate resistance loss: reduces power gain – Substrate loss: reduces power efficiency

Low-loss gate: Metal/Poly-Si damascene gate Al Al 300 nm 300 nm TiN TiN 50 nm 50 nm PolySi PolySi 50 nm 50 nm Gate Oxide Gate Oxide 20 or 30 nm 20 or 30 nm n - n - Advantages: – Implemented in the back end of process – Allows the use of Al or Cu: very low gate resistance – Self-aligned: no increase in overlap capacitance – Gate oxide undisturbed Achieved: 0.2 ohm/sqr (>10 for polySi, ~1 for silic’d gate)

Metal/Poly-Si Damascene Gate Source Gate Drain 3 μ m 200 μ m L g = 0.6 μ m f t ~ 15 GHz BV off > 18 V

Test chip 0.6 μ m minimum L g 10 mask levels 2 levels of metal Fabricated at MIT

Benefit of low gate resistance: small signal Source Gate Drain Source W f Damascene gate increases f max , enables wide gate fingers

Benefit of low gate resistance: large signal Source Gate Drain Source W f High PAE with gate finger width up to 140 μ m

Low-loss substrates: SOI and high-resistivity Si Gate Gate Gate Gate Gate Drain Drain Drain Drain Source Source Source Source Source Drain Drain Drain Drain Drain n - n - n - n - n - n + n + n + n + n + n + n + n + n + n + n - n - n - n + n + n + n - n - n + n + P P Gate Gate Gate Gate P P P Thin-film SOI Thin-film SOI Bulk Si Bulk Si Substrate: Handle wafer: • Regular Si • Regular Si • High-resistivity Si • High-resistivity Si

Impact of substrate • SOI improves PAE • High-resistivity silicon improves PAE on bulk • High-resistivity silicon does not improve PAE on SOI

Beyond 2 GHz Low-loss substrate very important at high frequencies

Analysis of substrate loss Source Drain Pad Gate Drain Loss Pad Loss • Pad Loss: • SOI effective • HR effective on bulk Si and SOI • Drain Loss: • SOI somehow effective • HR very effective on bulk Si, only moderately on SOI

Why is HRSOI Ineffective? Source Drain Pad Gate p n + n + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - C box HRSOI R surf R sub Surface inversion increases drain loss on HRSOI

Effect of substrate inversion in HRSOI-LDMOS 60 Load-Pull Measurement 55 2.4 GHz RF in RF out Peak PAE [%] 50 45 HRSOI 40 4.8 GHz + 35 - V HS 30 -30 -20 -10 0 10 20 30 V HS [V] • Eliminating substrate inversion improves PAE • Most prominent at high frequencies

Impact of inversion layer elimination 60 f=1.9 GHz Enhancement due to Peak PAE [%] 55 elimination of inversion layer 50 45 Bulk HR Bulk SOI HR SOI Substrate

Impact of inversion layer elimination • Eliminating substrate surface effects improves performance: – Particularly prominent in LDMOS due to large drain area – Both linear and saturated performance – Most prominent at high frequencies 65 14 60 60 V HS =5.5 V 12 50 55 peak PAE [%] 10 V HS = 5.5 V 40 50 V HS =0 V Gain [dB] PAE [%] 8 30 45 f = 4.8 GHz 6 V HS = 0 V 36x40 µm 20 40 Vdd = 3.6 V 4 Id = 10 mA 10 35 2 0 0 30 -10 -5 0 5 10 15 20 25 2 3 4 5 6 7 8 Output Power [dBm] Frequency [GHz]

Si MOSFETs for RF power GaAs HEMT 50 InP HEMT Si BJT SiGe HBT GaAs / InP HBT 40 GaAs MESFET GaN HEMT Output Power [dBm] LDMOS CMOS 30 20 10 0 0.1 1 10 100 1000 Frequency [GHz] 1. Extending LDMOS beyond 2 GHz 2. RF power suitability of deeply scaled CMOS

2. RF power suitability of deeply scaled CMOS (PhD Thesis of J. Scholvin) Attractiveness of CMOS: • System-on-Chip integration • Low cost • Low voltage • Good device models • Aggressive roadmap • Wide flavor of devices available Suitable for: • High-volume, low cost consumer applications 90 nm CMOS • Moderate frequencies (2-10 GHz) • Medium power (<100 mW) • Current: WLAN, Bluetooth, Cell-phone PA driver, WiMax/802.16 Picture from: http://www.intel.com/research/silicon/micron.htm#silicon

Issues of CMOS for RF power • Concerns: CMOS scaling ⇒ V dd ↓ ⇒ P out ↓ data for IEEE published CMOS PA devices and circuits • Possible solutions: – Raise V dd ⇒ impact on reliability – Use I/O devices ⇒ not really scaling

90 nm CMOS: there is a lot more than 90 nm devices! • Includes devices with longer gate lengths and thicker gate oxides for I/O drivers and high V operation • Designed RF power devices in collaboration with IBM Oxide thickness thin medium thick (14 A) (22 A) (51A) Nominal voltage [V] 1.0 1.2 2.5 L g = 90 nm x L g = 130 nm x x L g = 250 nm x x x

The benefits of scaling for RF 200 logic device 150 f max (GHz) 100 50 power device 0 90 nm 130 nm 250 nm Device type • Logic devices at optimized bias point have very high bandwidth • But… power devices at class AB bias point have much less bandwidth

RF power performance of standard 90 nm devices 70 1 cell 8 cells V dd = 1 V, I d = 26 mA/mm 60 f = 2.2 GHz 48x16 µm (1 cell) Gain [dB], PAE [%] 50 8 x 48x16 (8 cell) 40 30 PAE 20 Gain 10 0 -20 -10 0 10 20 30 P out [dBm] • 1 cell: Peak PAE = 66% at P out = 12.5 dBm • 8 cell: Peak PAE = 59% at P out = 20.2 dBm

Linear performance of 90 nm CMOS 70 0 60 PAE -20 50 -35 dBc -40 IM 3 [dBc] PAE [%] 40 IM 3 30 -60 20 V dd = 1 V -80 I d = 26 mA/mm 10 freq = 2.2 GHz WCDMA PA driver spec 8x48x16 µm 0 -100 -20 -10 0 10 20 30 P out [dBm] • What is PAE at a given IM 3 ? – at IM 3 = -35 dBc, PAE = 12% at P out = 12 dBm • Exceeds WCDMA PA driver specs

90 nm vs. 250 nm devices at 8 GHz 70 30 Lg = 90nm, Thin Ox Lg = 250nm, Thick Ox 60 25 PAE Output Power Density 50 Peak PAE [%] [dBm at 1 mm] 20 40 P out 30 15 20 10 freq = 8 GHz 10 I d = 26 mA/mm 0 5 0.1 1.0 10.0 V dd [V] • At V dd = 1 V, 90 nm has best PAE and P out • 250 nm device offers highest power density at V dd =2.5 V

90 nm vs. 250 nm 90 nm, thin oxide 250 nm, thick oxide V gs = 1V V gs = 2.4V 0.2V steps 0.1V steps • 250 nm thick oxide device has higher V ds,sat ⇒ compresses earlier and softer ⇒ lower P out and peak PAE • As V dd ↑ impact of V ds,sat decreases