Shaahin Hessabi Department of Computer Engineering Sharif University - - PowerPoint PPT Presentation

Shaahin Hessabi Department of Computer Engineering Sharif University of Technology

Requirements Requirements

Design‐for‐reuse is necessary for both memories and analog

circuits.

Both sensitive to noise and technology parameters.

h d d i d

Hence, hard cores or custom‐designed

Design‐for‐reuse for these circuits requires items described for

logic cores plus many additional rules and checks logic cores plus many additional rules and checks.

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Why Large Embedded Memories? Why Large Embedded Memories?

50‐ 60% of the SoC area is occupied by memories.

Multiple SRAMs, multiple ROMs, large DRAMs, flash memory blocks.

Modern microprocessors: more than 30% of the chip area is

i d b b dd d h

• ccupied by embedded cache.

Motivations of large embedded memories:

1

Reduction in cost and size by integration of memory on the chip

1.

Reduction in cost and size by integration of memory on the chip.

2.

On‐chip memory interface (replacing large off‐chip drivers with smaller

• n‐chip drivers)
• reduces capacitive load, power, heat, length of wire.
• achieving higher speeds.

3

Elimination of pad limitations of off chip modules and using a larger word

3.

Elimination of pad limitations of off‐chip modules and using a larger word width.

• higher performance.

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The Increasing Memory Content The Increasing Memory Content

20 80% 90% 100% 52 71 83 90 60% 70% 80% Memory 83 90 94 40% 50% y Reused Logic New Logic 10% 20% 30% 0% 10% 1999 2002 2005 2008 2011 2014

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I i f L M i h L i Integration of Large Memory with Logic

Adds significant complexity to

g p y the fabrication process

Increases mask counts

affects cost and memory density

impacts total capacity, timing

• f peripheral circuits and system
• f peripheral circuits, and system

performance.

If process optimized for logic

p p g to obtain performance:

high saturation current prohibits

ti l t i t a conventional one‐transistor DRAM cell.

the 4T cell: simple, good

performance, large area

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I i f L M i h L i Integration of Large Memory with Logic

If optimized for DRAM with

p very low leakage current:

performance (switching speed)

f h l ff

• f the logic transistor suffers.

1T cell is used, which allows area

• ptimization, but requires a

p , q complex voltage regulator and dual‐gate process

Provides approximately half the Provides approximately half the

performance of previous scheme.

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Integration of Large Memory with Logic Integration of Large Memory with Logic

Solution: dual‐gate processes

2 different types of gate oxides optimized for DRAM and logic transistors. logic and memory fabricated in different parts of the chip, each using its

• wn set of technology parameters
• wn set of technology parameters.

If flash memory used: double poly‐silicon layers required.

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Basic Structures

6T SRAM ll 4T DRAM cell 6T SRAM cell 3T DRAM cell 4T DRAM cell 1T Flash cell

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1T DRAM cell 1T Flash cell

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B i St t Basic Structures

2‐port memory

2 independent single‐ended reads or one differential write. 2 reads and one write by time multiplexing y p g Read during φ1, write during φ2

Content‐Addressable Memory (CAM) y ( )

Used in caches. Read and Write cycles: like before… Match c cle place data on bit lines but don’t Match cycle: place data on bit lines but dont assert word line. The word match lines from the CAM array can be used as WORD lines in a companion RAM to be used as WORD lines in a companion RAM to read out other data associated with the tag stored in the CAM. Uses: fully‐associative caches translation

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Uses: fully associative caches, translation lookaside buffers (TLBs), ...

M C il Memory Compiler

provide a framework that provide a framework that

includes physical, logical, and electrical representations of p the design database.

Linked with front‐end design

tools and generate data that is readable with back‐end tools.

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IP Generator/Compiler IP Generator/Compiler

User specifies

Power dissipation, code size, application performance, die size Types, numbers and sizes of functional unit, including processor User defined instructions User‐defined instructions.

Tool generates

RTL code diagnostics and test reference bench RTL code, diagnostics and test reference bench Synthesis, P&R scripts Instruction set simulator, C/C++ compiler, assembler, linker, debugger,

profiler, initialization and self‐test code

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T d f Mi d Si l S C Trends for Mixed‐Signal SoCs

Real world signals are analog Real world signals are analog Information processing and

computing are in digital computing are in digital

Problem: Analog and digital

circuits often don’t get along circuits often dont get along together!

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The Substrate Crisis The Substrate Crisis

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l l Digital Noise Coupling

Fast transients in Switching noise in digital circuits g analog circuits Who needs to consider the substrate coupling noise impact?

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Sources of Substrate Noise Sources of Substrate Noise

Inductive Noise (di/dt, 100 mV)

Bonding wires Large di/dt on power supplies Non ideal power supplies connecting directly to the substrate Non‐ideal power supplies connecting directly to the substrate

Capacitive Coupling (dv/dt, 10 mV)

Interconnect capacitance to substrate Interconnect capacitance to substrate Junction capacitances

Impact Ionization (Idrain, Vgs & Vds, 2 mV)

p ( drain,

gs ds,

)

High electric field near the drain of saturated MOS devices Substrate current injection

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I d ti N i Inductive Noise

L changes with:

Type of package Type of package Number of pins for a connection

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C iti N i Capacitive Noise

Large capacitance to substrate (supply, buses, output

drivers, clock, etc.) , , )

Shielding reduces some values

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Primary Noise Sources Primary Noise Sources

Logic power rail bounce due to driver switching Chip substrate coupling Package resonance (excited by overtones of clock) Analog power rail bounce Noise coupling to various isolated device structures is proportional

to the capacitance from that device to chip substrate.

No effective shielding techniques. S

ti f i t itt f i i k littl diff i

Separation of noise transmitter from noise receiver makes little difference in

coupled noise due to low substrate resistance (for heavily doped substrate)

Noise is linear with switching power on‐chip.

Noise is linear with switching power on chip.

Noise peak voltage increases as logic transitions are synchronized

for a given amount of switching power. Noise energy unchanged. g g p gy g

Noise energy proportional to logic power rail inductance.

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Primary Noise Sources (cont’d) Primary Noise Sources (cont d)

Synchronous noise

Using single clock for switching functions. Can excite the package system resonance in phase with analog sampling

clock clock.

Its effect can be a DC shift in the sampled signal with a given noise excitation level.

Pseudo‐synchronous noise

Mainly due to package resonance when excited by the CMOS switching. If clock frequency is at the package resonant frequency the noise will

increase dramatically One must lower the Q by increasing damping increase dramatically. One must lower the Q by increasing damping.

Asynchronous noise

Noise from mixing clocks Will start chip‐package‐PCB system resonating on Noise from mixing clocks. Will start chip‐package‐PCB system resonating on

the asynchronous clock edges. The asynchronous clocks will also couple this noise to the chip substrate and therefore to the analog circuits.

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RF IC P bl RF IC Problem

Weak signals at RF input (μV)

g p (μ )

Several on‐chip noise

mechanisms must be controlled

Linear and non‐linear mixing

and alaising with sampling of different noise sources

Coupled noise will manifest at different frequencies (e.g.

Coupled noise will manifest at different frequencies (e.g. phase noise due to low frequency modulation of transistors) and analysis/simulation especially complicated.

Small signal conventional analysis may not be adequate.

High integration: both analog (like VCOs, A/D), and digital

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(A/D, DSP) may exists on the same chip.

S b N i I j i M h i Substrate Noise Injection Mechanisms

Capacitive injection

p j through reverse‐biased junctions

Noise injection through

contacts

Other mechanisms:

d l Noise in mixed signal systems

Parasitic capacitance between an interconnect and the substrate The forward biasing of device junctions Hot carriers – the high electric field between drain and source in submicron transistors Ionization currents (f<100MHz) is the most important of

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( ) p substrate coupling sources.

Chip/Package Model for Noise Analysis Chip/Package Model for Noise Analysis

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Substrate Noise Reduction Substrate Noise Reduction

• 1. Wafer and process level solutions
• 2. Physical and Layout Level Solutions
• 3. Circuit Level Solutions: Robust Circuits and Frequency Planning
• 4. Package and Board Level Solutions: High Quality Power

Distribution Network Design

• Decoupling,
• Power distribution,
• Turn off functions not in use
• Turn off functions not in use
• 5. System Level Solutions: SoC vs SiP

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1 W f /P L l S l ti

• 1. Wafer/Process Level Solutions

Lightly doped Drain MOSFET

g y p

Lower impact ionization currents

Current is due to high electric field near

th d i f t t d MOS the drain of saturated MOS

SOI process

Capacitive shielding of low‐frequency Capacitive shielding of low‐frequency

coupling

Minimize supply inductance Minimize supply inductance

Multiple bond‐wire/package pins Distribute power supply pins on chip/package

p pp y p p p g

…

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2 Physical and Layout Level Solutions

• 2. Physical and Layout Level Solutions

Package inductance needs to be minimized for power supplies

d l d b directly connected to substrate

Use separate power supply for largest current drivers

Seal and pad rings affect noise transfer Seal and pad rings affect noise transfer Digital signals should not

Be routed over or through the analog portion of the chip Be routed over or through the analog portion of the chip Be routed next to sensitive lines

Floorplan such that the package pin assignments do not route

Floorplan such that the package pin assignments do not route sensitive analog signals near digital I/Os, supplies, or clock signals

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Layout Layout

Digital layout: made by interconnecting simple blocks (place cells

d b h ) and route between them).

Design criteria: minimize area and signal delay.

A

l l t t i t k ith li it d l it l

Analog layout contains networks with limited complexity, rarely

reuse specific cells, involves optimizing transistor layouts with much less concern for interconnections. much less concern for interconnections.

Design criteria: accuracy and noise immunity.

Mixed analog digital layout: the main issue is the substrate

g g y coupling noise.

Design criteria: careful circuit design and strict layout.

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3 Circuit Level Solutions

• 3. Circuit Level Solutions

a.

Circuit Design for Robustness

• b. Frequency Planning

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3 a Circuit Design for Robustness 3.a. Circuit Design for Robustness

Low noise logic

Current steering logic (CSL, …) Minimize switch currents in power supply

C

t ll d i it ti i

Controlled circuit timing

Analog sampling away from clock instants

Fully differential analog circuitry Fully differential analog circuitry

High common mode rejection High power supply rejection

g p pp y j

Ensure layout symmetry w.r.t. noise source

Minimize the instantaneous current

Slow rise and fall times Stagger the timing of output drivers or large blocks of circuitry

h l

Lower the voltage swing

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3 b Frequency Planning 3.b. Frequency Planning

Main peaks in substrate noise come from:

Power/ground distribution resonance Circuit switching (signal rise edge), clock

Id

C f l f l i f RF/A l i it i d t

Idea: Careful frequency planning for RF/Analog circuits in order to

avoid these noise peaks.

Solutions: Solutions:

Place decoupling capacitors, change power/ground pin allocation to reduce

and move the frequency of resonance

Use differential circuits to avoid common‐mode ground noise

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Analog Circuits Analog Circuits

Almost 5% of SoC area. Primary design issue: precise specifications of various parameters Tools such as MATLAB are used for specification and simulation. Verilog‐AMS and VHDL‐AMS are increasingly used for modeling. Automatic generation from AMS‐HDL is still in its infancy,

because of the large number of variables associated with AMS design.

Current use of AMS‐HDLs for ESL: system level verification.

requires co‐simulation of analog and digital behavioral models to reduce

simulation costs.

AMS blocks cannot be easily synthesized from a high‐level AMS blocks cannot be easily synthesized from a high‐level

specification without low‐level support.

Must follow a design process such as the firm IP flow, shown at next slide.

g p ,

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AMS IP D i Fl AMS IP Design Flow

Starting point: set of library

g p y components that comprise the un‐optimized schematic view

• f the design.

Library consists of parameterized

reusable components reusable components.

Model parameters are set by

an optimization tool. p

Refer to lecture 6 for further

issues on analog cores. g

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D t t Data converters

Data converters (ADCs and DACs): key blocks in AMS SoCs Data converters (ADCs and DACs): key blocks in AMS SoCs.

Act as Mixed‐Signal Interfaces

ADC:

ADC:

DAC:

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Issues in AMS SoCs Issues in AMS SoCs

Important issues:

Technology, architecture, implementation choices (SoC, SoP)

Technology choices:

C OS hi h d i d i i i i

CMOS: high speed, poor noise, poor transconductance, poor intrinsic gain Bipolar: high speed, good noise and transconductance, better intrinsic gain SiGe: high speed good noise and transconductance best intrinsic gain SiGe: high speed, good noise and transconductance, best intrinsic gain,

expensive

GaAs: for high speed, special applications, very expensive.

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Technology Choice Technology Choice

CMOS is the most popular technology. Reasons: Cheap technology Very good for digital circuits, good for analog circuits. Scaling in CMOS technology

Improves device performance: speed and power efficiency (gm/ID) sub 45nm. A lot of design challenges

Integration with high density digital circuits: possibility of placing

both analog and digital components on the same chip both analog and digital components on the same chip.

improves overall performance and/or reduce the cost.

The trend is to use smart techniques to enhance the RF/AMS The trend is to use smart techniques to enhance the RF/AMS

circuits performance (offset, accuracy, linearity)

Digitally enhanced analog

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T h l S li Technology Scaling

Analog circuits: highly

g g y susceptible to random variations in process and operating conditions conditions.

Such variations do not scale with

process. ll h f h

All these factors increase the power

dissipation and the manufacturing costs.

Increase in relative performance

is behind the digital circuits performance performance

doubles in 5 years

Over 15 years, analog/digital

f i performance gap is ~ 150x.

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