Testability L Lecture 7: Fault Simulation t 7 Shaahin Hessabi - - PowerPoint PPT Presentation

Testability L t 7 Lecture 7: Fault Simulation

Shaahin Hessabi Shaahin Hessabi Department of Computer Engineering Sharif University of Technology

Adapted from the presentation prepared by book authors

Slide 1 of 31 Sharif University of Technology Lecture 6: Fault Simulation

O tli Outline

Problem and motivation Fault simulation algorithms

Serial Parallel Parallel Deductive Concurrent

Random Fault Sampling Summary

Slide 2 of 31 Sharif University of Technology Lecture 6: Fault Simulation

Problem and Motivation

Fault simulation Problem:

Given:

A circuit A sequence of test vectors A fault model A fault model

Determine:

Fault coverage: fraction (or percentage) of modeled faults detected by test vectors Set of undetected faults (for test generation)

Motivation

Determine test quality and in turn, product quality Find undetected fault targets to improve tests Construct fault dictionary for diagnosis Construct fault dictionary for diagnosis

– Use a fault simulator to compute & store the response for every fault – If the output response of the circuit under test matches any of the

response in the fault dictionary the fault location is identified

Slide 3 of 31 Sharif University of Technology Lecture 6: Fault Simulation

response in the fault dictionary, the fault location is identified

Yield and Defect Level

Let:

Y (yield): probability that a manufactured circuit is defect-free Y (yield): probability that a manufactured circuit is defect free DL (defect level): probability of shipping a defective product d (defect coverage): the defect coverage of the test used to check for

manufacturing defects manufacturing defects

D = 1 Y1-d

Defec

DL = 1- Y1 d

approximate defect coverage with fault coverage

ct Level

with fault coverage

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Defect Coverage %

High Fault Coverage: Why? g g y

Slide 5 of 31 Sharif University of Technology Lecture 6: Fault Simulation

Fault Coverage vs. Defect Coverage

High fault coverage (measured for SSFs) is:

g g ( )

necessary but not sufficient

for high defect coverage.

Also need:

Parametric testing Delay-fault testing Bridging fault testing Bridging-fault testing Technology-specific-fault testing (e.g., CMOS stuck-open faults)

Slide 6 of 31 Sharif University of Technology Lecture 6: Fault Simulation

Fault simulator in a VLSI Design g Process

Verified design netlist Verification input stimuli Fault simulator Test vectors Modeled fault list Test compactor Remove tested faults

Delete vectors

Test Fault Low generator coverage ? Add vectors Adequate

Slide 7 of 31 Sharif University of Technology Lecture 6: Fault Simulation

q Stop

Fault Simulation Scenario au t S u at o Sce a o

Circuit model: mixed-level

Mostly logic with some switch level for high impedance (Z) and Mostly logic with some switch-level for high-impedance (Z) and

bidirectional signals

High-level models (memory, etc.) with pin faults

Signal states: logic

Two (0, 1) or three (0, 1, X) states for purely Boolean logic circuits Four states (0, 1, X, Z) for sequential MOS circuits

Timing:

Zero-delay for combinational and synchronous circuits Mostly unit-delay for circuits with feedback

Slide 8 of 31 Sharif University of Technology Lecture 6: Fault Simulation

Fault Simulation Scenario (cont’d) Fault Simulation Scenario (cont d)

Faults:

Mostly single stuck-at faults Sometimes stuck-open, transition, and path-delay faults; analog

i it f lt i l t t t i circuit fault simulators are not yet in common use

Equivalence fault collapsing of single stuck-at faults Fault-dropping: a fault once detected is dropped from consideration Fault dropping: a fault once detected is dropped from consideration

as more vectors are simulated; fault-dropping may be suppressed for diagnosis F lt li d l f f lt i i l t d h th

Fault sampling: a random sample of faults is simulated when the

circuit is large

Slide 9 of 31 Sharif University of Technology Lecture 6: Fault Simulation

F lt Si l ti Al ith Fault Simulation Algorithms

Serial

P ll l

Parallel Deductive

C t

Concurrent

Slide 10 of 31 Sharif University of Technology Lecture 6: Fault Simulation

Serial Algorithm

Algorithm: Simulate fault-free circuit and save responses.

Repeat following steps for each fault in the fault list: Repeat following steps for each fault in the fault list:

Modify netlist by injecting one fault Simulate modified netlist, vector by vector, comparing responses

y p g p with saved responses

If response differs, report fault detection and suspend simulation of

remaining vectors remaining vectors

Advantages:

Easy to implement; needs only a true-value simulator less memory Easy to implement; needs only a true value simulator, less memory Most faults, including analog faults, can be simulated

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Serial Algorithm (Cont.)

Disadvantage: Much repeated computation; CPU time

g p p prohibitive for VLSI circuits

Alternative: Simulate many faults together

Test vectors Fault-free circuit Comparator f1 detected? Circuit w ith fault f1 Comparator f2 detected? Circuit w ith fault f2 Circuit w ith fault fn Comparator fn detected?

Slide 12 of 31 Sharif University of Technology Lecture 6: Fault Simulation

Parallel Fault Simulation

Compiled-code method; best with two-states (0,1) Exploits inherent bit-parallelism of logic operations on

computer words

Storage: one word per line for two-state simulation; i.e.,

fixed low memory requirement M lti i l ti E h i l t 1

Multi-pass simulation: Each pass simulates w -1 new

faults, where w is the machine word length

Speed up over serial method

w 1

Speed up over serial method ~ w -1 Not suitable for circuits with timing-critical and non-

Boolean logic Boolean logic

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Parallel Fault Simulation Example Parallel Fault Simulation Example

Bit 0: fault-free circuit Bit 1: circuit with c s-a-0 Bit 2: circuit with f s-a-1

a

1 1 1 1 0 1

c s-a-0 detected

b c e g

1 1 1 1 0 1 1 0 1 s-a-0

d f g

0 0 0 s-a-1 1

d f

s a 1 0 0 1

Slide 14 of 31 Sharif University of Technology Lecture 6: Fault Simulation

Parallel Fault Simulation- Multiple Values

Three signal values : { 0 1 u }

A A1 A0

Three signal values : { 0, 1, u } Two bits per signal encoding:

A A1 A0 1 1 1 U 1

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Deductive Fault Simulation Deductive Fault Simulation

One-pass simulation

p

Each line k contains a list Lk of faults detectable on k;

i.e., fault F in list Lk ⇔ F causes signal k be sensitized

k

Following true-value simulation of each vector, fault lists

• f all gate output lines are updated using set-theoretic

rules, signal values, and gate input fault lists

PO fault lists provide detection data Limitations:

Set-theoretic rules difficult to derive for non-Boolean gates

G t d l diffi lt t

Gate delays are difficult to use

Slide 16 of 31 Sharif University of Technology Lecture 6: Fault Simulation

Deductive Fault Simulation (cont’d)

AND gate

• Any fault causes an error at A or B (change A or B

from 1 to 0) will cause Z to be erroneously 0. LZ = LA ∪ LB ∪ {Z s-a-0}

Z A B

{ }

Any fault that causes A to be 1 without changing B,

will cause Z to be in error ; i e Z 1 will cause Z to be in error ; i.e, Z = 1 LZ = (LA ∩ L’B) ∪ {Z s-a-1} = (LA − LB) ∪ {Z s-a-1}

Slide 17 of 31 Sharif University of Technology Lecture 6: Fault Simulation

Deductive Fault Simulation (cont’d)

Gate Z:

I f i

I: set of inputs c: controlling value i: inversion i: inversion S: set of inputs with values c

The fault list of Z:

If no input has value c, any fault effect on any input propagates to the

• utput.

p

If some inputs have value c, only a fault effect that affects all the inputs

at c without affecting any of the inputs at c propagates to the output.

Slide 18 of 31 Sharif University of Technology Lecture 6: Fault Simulation

Deductive Fault Simulation (Example) ( p )

Notation: Lk is fault list for line k kn is s-a-n fault on line k a

1 {a0} Le = La U Lc U {e0} = {a0 , b0 , c0 , e0}

b b c c e e g g

1 1 1 {b0 , c0} {b0}

d d f f g

{b0 , d0} Lg = (Le Lf ) U {g0} { } U {b0 , d0} = {a0 , c0 , e0 , g0} {b0 , d0 , f1}

Faults detected by the input vector

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the input vector

Concurrent Fault Simulation

Event-driven simulation of fault-free circuit and only those

parts of the faulty circuit that differ in signal states from the parts of the faulty circuit that differ in signal states from the fault-free circuit.

A list per gate containing copies of the gate from all faulty A list per gate containing copies of the gate from all faulty

circuits in which this gate differs. List element contains fault ID, gate input and output values and internal states, if any. , g p p , y

All events of fault-free and all faulty circuits are implicitly

simulated.

Faults can be simulated in any modeling style or detail

supported in true-value simulation (offers most flexibility.)

Faster than other methods, but uses most memory.

Slide 20 of 31 Sharif University of Technology Lecture 6: Fault Simulation

Concurrent Fault Simulation (Cont’d)

An element contains:

Fault index

F lt t t

Fault state

• Input values
• Output values
• Output values

Event-driven: events include value changes in both fault-

free and faulty circuits. y

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Concurrent Fault Simulation Example Concurrent Fault Simulation Example

a0 b0 c0 e0

1 1 1 1 1 1

a0 b0 c0 e0

a a b c c e e

1 1 1 1 1 1 1 1

c c d d f f g

1 1 1 0

a0 b0 c0 e0

d d f f

1 1 1 1 1 1 1 1 1 0 1 0 1 1 1

b0 d0 d0 g0 f1 f1

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0 1 1 1

Concurrent Fault Simulation - Convergence

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Concurrent Fault Simulation - Divergence

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Comparing Fault Simulating Methods

Criteria: ability to handle :

(A) Multiple signal values (B) Different levels of abstraction (C) Accurate timing (C) Accurate timing

Rank order by criteria

Parallel Deductive Concurrent (A) 2 3 1 (A) 2 3 1 (B) 2 2 1 (C) 2 2 1 (C) 2 2 1

Slide 25 of 31 Sharif University of Technology Lecture 6: Fault Simulation

Disadvantages of Deductive & g Concurrent Algorithms

Large memory to record the status of all machines

Dynamic memory, (linked lists)

y y, ( )

Evaluation overhead on the linked lists Performance overhead in memory management

y g

Slide 26 of 31 Sharif University of Technology Lecture 6: Fault Simulation

Fault Sampling p g

A randomly selected subset (sample) of faults is simulated.

y ( p )

Measured coverage in the sample is used to estimate fault

coverage in the entire circuit.

Advantage: Saving in computing resources (CPU time and

memory.)

Disadvantage: Limited data on undetected faults.

Slide 27 of 31 Sharif University of Technology Lecture 6: Fault Simulation

Motivation for Sampling p g

Complexity of fault simulation depends on:

Number of gates Number of faults Number of faults Number of vectors

Complexity of fault simulation with fault sampling depends Complexity of fault simulation with fault sampling depends

• n:

Number of gates Number of vectors

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Random Sampling Model p g

Detected Undetected All faults w ith fault fault a fixed but unknow n coverage Random picking coverage Np = total number of faults (population size) Ns = sample size N << N (population size) C = fault coverage (unknow n) Ns << Np c = sample coverage (a random variable) ( )

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Probability Density of Sample Coverage, c

(x--C )2 (x C )

• - ------------

1 2σ 2 p (x ) = Prob(x < c < x +dx ) = -------------- e p (x ) Prob(x < c < x dx )

e

σ (2 π) 1/2

1/2

cf: page 122 of the text

) C (1 - C) Variance riance, σ 2 = ------------ N Sampling p (x ) Ns Mean = C Sampling error σ σ C C +3σ C -3σ 1.0 x x

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Sample coverage

Sampling Error Bounds p g

Variance of C: C (1 - C ) | x C | = 3 [

] 1/2

Sampling error: | x - C | = 3 [ -------------- ] Ns Solving the quadratic equation for C, we get the 3-sigma (99.7% confidence) estimate: Sampling error: confidence) estimate: 4.5 C 3σ = x ± ------- [1 + 0.44 Ns x (1 - x )]1/2

3σ s

Ns Where Ns is sample size, x is the measured fault coverage in the sample. f f f % Example: A circuit with 39,096 faults has an actual fault coverage of 87.1%. The measured coverage in a random sample of 1,000 faults is 88.7%. The above formula gives an estimate of 88.7% ± 3%. CPU time for sample

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simulation was about 10% of that for all faults.