Digital Testing Digital Testing Lecture 9 : Combinational - - PowerPoint PPT Presentation

Digital Testing Digital Testing Lecture 9 : Combinational Automatic Test Pattern Automatic Test-Pattern Generation (ATPG) Basics Generation (ATPG) Basics

Instructor: Shaahin Hessabi Instructor: Shaahin Hessabi Department of Computer Engineering Sharif University of Technology S U y gy Adapted with modifications from lecture notes prepared by the book authors

Sharif University of Technology Testability: Lecture 9 1

Outline

Structural vs. functional test C mpl t n Completeness Aspects of Test Generation Test Generation Approaches

Ad-Hoc Exhaustive testing Fault table analysis Boolean difference method Boolean difference method (Pseudo) random test generation Fault-oriented deterministic methods Fault-independent deterministic methods

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Origins of Stuck Faults Origins of Stuck-Faults

Eldred (1959) – First use of structural testing for

the Honeywell Datamatic 1000 computer y p

Galey, Norby, Roth (1961) – First publication of

stuck-at-0 and stuck-at-1 faults stuck-at-0 and stuck-at-1 faults

Seshu & Freeman (1962) – Use of stuck-faults

for parallel fa lt sim lation for parallel fault simulation

Poage (1963) – Theoretical analysis of stuck-at

f l faults

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F ti l St t l ATPG Functional vs. Structural ATPG

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Carry Circuit Carry Circuit

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Functional vs Structural(Cont’d) Functional vs. Structural(Cont’d)

Functional ATPG: generate complete set of tests for circuit

g p input-output combinations. For the adder example:

129 inputs, 65 outputs: 2129 = 680 564 733 841 876 926 926 749 214 863 536 422 912 patterns 2129 = 680,564,733,841,876,926,926,749,214,863,536,422,912 patterns Using 1 GHz ATE, would take 2.15 x 1022 years Structural test: No redundant adder hardware, 64 bit slices Each with 27 faults (using fault equivalence) At most 64 x 27 = 1728 faults (tests) ( ) Takes 0.000001728 (1.7 μ sec) on 1 GHz ATE Designer gives small set of functional tests; augment with

t t l t t t b t t 98+ % structural tests to boost coverage to 98+ %

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Definition of Automatic Test-Pattern Generator

Operations on digital hardware: Operations on digital hardware: Inject fault into circuit modeled in computer Use various ways to activate and propagate fault effect through h d t i it t t hardware to circuit output Output flips from expected to faulty signal Electron-beam (E-beam) test observes internal signals: Electron beam (E beam) test observes internal signals:

“picture” of nodes charged to 0 and 1 in different colors

Too expensive Scan design: add test hardware to all flip-flops to make them a

giant shift register in test mode

C hift t t i t t t Can shift state in, scan state out Widely used; makes sequential test combinational Costs: 5 to 20% chip area, circuit delay, extra pin, longer test sequence

Sharif University of Technology Testability: Lecture 9

p y p g q

Slide 7 of 45

Circuit and Binary Decision Tree

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Binary Decision Diagram Binary Decision Diagram

BDD – Follow path from source to

sink node – product of literals along path gives Boolean value at sink

Rightmost path: A B C = 1 Problem: Size varies greatly

with variable order with variable order

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Algorithm Completeness go t Co p ete ess

Definition: Algorithm is complete if it ultimately Definition: Algorithm is complete if it ultimately

can search entire binary decision tree, as needed, to generate a test to generate a test

Untestable fault: no test for it, even after entire

tree searched tree searched

Combinational circuits only: untestable faults are

d d h i h f redundant, showing the presence of unnecessary hardware

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Combinational Test Generation Combinational Test Generation

We discuss testing for SSF with the following

assumptions: off-line, edge-pin, stored-pattern testing with full comparison of the output results.

Given

a logical fault model, and a circuit,

determine

a small set of test vectors that detects all faults in the circuit.

Under the stuck-at fault model, the problem is NP-

p complete for combinational circuits

However, test generators that efficiently generate tests for 1M-gate

Sharif University of Technology Testability: Lecture 9

circuits are in use today.

Slide 11 of 45

Test Generation Process

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Aspects of Test Generation Aspects of Test Generation

1 The cost of TG 1. The cost of TG

• Depends on the complexity of the TG method; e.g., Random TG

(RTG) is simple. However:

a.

Needs a large set of random vectors to achieve high fault

• coverage. The required fault simulation might be an

expensive process expensive process.

b.

Longer test ⇒ Higher cost to apply (increases time of testing equipment, and memory requirement for tester).

• Random vectors are often generated on-line by hardware and

used with compact testing.

• TG cost also depends on the complexity of CUT
• TG cost also depends on the complexity of CUT.
• DFT techniques reduce the CUT complexity for testing

purposes.

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Aspects of Test Generation (cont’d) Aspects of Test Generation (cont’d)

• 2. The quality of the generated test
• Normally measured by fault coverage determined by fault
• Normally measured by fault coverage, determined by fault

simulation.

• Deterministic TG produces shorter and higher-quality tests

(w.r.t. RTG), by taking into account the function or the structure

• f the CUT.

3 Th t f l i th t t (ti d

• 3. The cost of applying the test (time and memory

requirements of the tester)

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Test Generation Approaches Test Generation Approaches

1 Ad-Hoc 1. Ad-Hoc 2. Exhaustive testing 3. Fault table analysis 4. Boolean difference method 5. (Pseudo) random test generation 6 Fault-oriented deterministic methods: 6. Fault oriented deterministic methods:

a. D-algorithm [Roth 1968] b. PODEM [Goel 1981] [ ]

7. Fault-independent deterministic methods:

• Critical path method

Sharif University of Technology Testability: Lecture 9

p

Slide 15 of 45

• 1. Ad-Hoc

Uses functional test vectors developed by designers for

functional verification and design debugging by: functional verification and design debugging by:

Fault simulating to determine fault coverage Determining locations of undetected faults Adding additional functional tests to exercise areas of design with undetected faults Re-fault simulating and repeating until desired fault coverage is g g g achieved

No special test generation system is required, only fault

i l simulator

Utilizes existing vectors and designer expertise Achieving high fault coverage may be difficult and time

consuming, specially for synthesized designs.

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• 2. Exhaustive Testing
• 2. Exhaustive Testing

Applying all possible 2n possible input patterns

pp y g p p p p

Satisfactory for small circuits only. Infeasible, unless circuit is partitioned into cones of logic, with less than 15 inputs (pseudo- exhaustive testing) exhaustive testing)

Perform exhaustive ATPG for each cone Misses faults that require specific activation patterns for multiple

cones to be tested

Assuming a tester capable of applying a test pattern

l l h every 100ns (10 MHz), we can calculate the test time as shown in table 1.

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2 Exhaustive Testing (cont’d)

• 2. Exhaustive Testing (cont d)

Inputs # of Tests Test Time Inputs # of Tests Test Time

20 220 ≈ 106 0.1 sec 40 240 ≈ 1012 30.5 hours 60 260 ≈ 1019 58500 years

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• 3. Fault Table Analysis

y

Fault Table example

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Fault Table Analysis (cont’d) Fault Table Analysis (cont d)

d d b Reduced fault table after “fault collapsing” Conclusion: 5 tests are needed of which 3 are needed, of which, 3 are essential.

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• 4. Boolean Difference Method
• The Boolean difference of F(x1 ,x2 ,…,xn ) = F(X) w.r.t. (with

respect to) x1 is: dF(X)/dx1 = F(0, x2 ,…,xn) ⊕ F(1, x2 ,…,xn)

• F(0, x2 ,…,xn) and F(1, x2 ,…,xn) are the cofactors of F(X) w.r.t. x1
• To test for fault x1 /0 (x1 /1):

1

( 1

1. Apply 1 (0) to input line x1 2. Assign 0/1 values to x2 ,…,xn that make the output signal F(X) sensitive to change in x1; i e make dF(X)/dx1 = 1 change in x1; i.e., make dF(X)/dx1 1

• Represent the tests for a fault on input line xi of C by the Boolean

function T whose minterms correspond to the test patterns. Then: p p

T for xi/0 = xi.dF(X)/dxi T for xi/1 = xi’.dF(X)/dxi

• If the faulty line h is an internal line of C replace x by h(X) and
• If the faulty line h is an internal line of C, replace xi by h(X), and

F(X) by F*(X,h) in the above formulas.

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Boolean Difference Symbolic Method y (Sellers et al.)

g = G (X1, X2, …, Xn) for the fault site fj = Fj (g, X1, X2, …, Xn) 1 j

≤ ≤

1 j m Xi = 0 or 1 for 1 i n

≤ ≤ ≤ ≤

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Boolean Difference Example Boolean Difference Example

Fault = a/1

/ F(a,b,c,d) = (a + bc)(b' + c')d' Ta/1 = a'.dF/da

a/1

/ dF/da = [1(b' + c')d' ⊕ bc(b' + c')d'] = b'd' + c'd' So Ta/1 = a'b'd' + a'c'd' Test set for a/1 = {0000 0010 0100} b d c d Test set for a/1 = {0000, 0010, 0100}

Sharif University of Technology Testability: Lecture 9 Page 23 of 41

Boolean Difference Example Boolean Difference Example

Fault = β/0 Tβ/0 = β (X).dF(X, β)/dβ β β β β(X) = a + bc F(X, β) = (b' + c')d' β dF/dβ= (b' + c')d' S T b'd' + 'd' So Tβ/0 = ab'd' + ac'd' Test set for β/0 = {1000,1010,1100}

Sharif University of Technology Testability: Lecture 9 Page 24 of 41

5 (Pseudo) Random Test Generation

• 5. (Pseudo) Random Test Generation

Simply generate an input vector using a pseudorandom

number generator and perform fault simulation to d t i if it d t t th t t fil determine if it detects the target file.

The characteristics of the fault greatly influence how

ll d d t t ti ill k well pseudorandom test generation will work

Easy-to-detect faults Hard-to-detect faults Hard to detect faults

Typically used in the beginning of the test generation

process to remove easy-to-detect faults from the fault p y list.

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(Pseudo) Random Test Generation

(cont’d)

F lt b f d d t t t Fault coverage vs. number of pseudorandom test vectors

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Path Sensitization Methods: Circuit Example

1 F

lt S iti ti

1 Fault Sensitization 2 Fault Propagation 3 Line Justification

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Path Sensitization Method: Circuit Example

Try path f – h – k – L blocked at j, since there is

no way to justify the 1 on i no way to justify the 1 on i

D 1 1 D D D D 1 D 1

Sharif University of Technology Testability: Lecture 9 Slide 28 of 45

Path Sensitization Method: Circuit Example (cont’d)

Try simultaneous paths f h k L and

g i j k L

Try simultaneous paths f – h – k – L and g – i – j – k – L

blocked at k because D-frontier (chain of D or D’) disappears D 1 1 D D 1 D D D 1

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Path Sensitization Method: Circuit Path Sensitization Method: Circuit Example (cont’d)

Final try: path g – i – j – k – L – test found!

D 1 D D D D D 1 1

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Computational Complexity Computational Complexity

Ibarra and Sahni analysis – NP-Complete

(no polynomial expression found for compute time, presumed to be exponential)

Worst case:

no pi inputs, 2 no_pi input combinations no_pi inputs, 2 input combinations no_ff flip-flops,4 no_ff initial FF states ( d hi 1 b d hi 1)

×

(good machine 0 or 1 bad machine 0 or 1) work to forward or reverse simulate n logic gates ∝ n

i ff

×

Complexity: O (n x 2 no_pi x 4 no_ff)

Sharif University of Technology Testability: Lecture 9 Slide 31 of 45

History of Algorithm Speedups History of Algorithm Speedups

Algorithm Est speedup over D-ALG Year Algorithm D-ALG

• Est. speedup over D ALG

(normalized to D-ALG time) 1 Year 1966 PODEM FAN TOPS 7 23 292 1981 1983 1987 TOPS SOCRATES Waicukauski et al 292 1574 ATPG System 2189 ATPG System 1987 1988 1990 † † Waicukauski et al. EST TRAN 2189 ATPG System 8765 ATPG System 3005 ATPG System 1990 1991 1993 † † † Recursive learning Tafertshofer et al. 485 25057 1995 1997

Sharif University of Technology Testability: Lecture 9

†:ATPG System

Slide 32 of 45

6 Fault Oriented ATPG

• 6. Fault-Oriented ATPG

Procedure Test (...) ( ) begin repeat repeat begin Select uncovered fault f ; Select uncovered fault f ; Generate test for f ; E l f l Evaluate current fault coverage; end; until (coverage ≥ c or time runs out) end

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Fault Oriented ATPG (cont’d) Fault-Oriented ATPG (cont d)

• Two fundamental steps in generating a test for a fault l
• Two fundamental steps in generating a test for a fault l

s-a-v:

1 Activate (excite) the fault; i e set PI values that cause line l to 1. Activate (excite) the fault; i.e., set PI values that cause line l to have value v’ (an instance of the line-justification problem). 2. Propagate the resulting error to a PO (uses line-justification for b k d i l ti ) backward simulation).

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Fault-Oriented ATPG (cont’d) ( )

Sharif University of Technology Testability: Lecture 9 Page 35 of 41

D Notation D Notation

D = 1 in good (fault-free) circuit; D = 0 in faulty circuit D 1 in good (fault free) circuit; D 0 in faulty circuit D’ = 0 in good (fault-free) circuit; D’ = 1 in faulty circuit Errors such as 0 / 1 in the following figure are denoted by the Errors such as 0 / 1 in the following figure are denoted by the

discrepancy values D and D’

Sharif University of Technology Testability: Lecture 9 Page 36 of 41

D Notation (cont’d) ( )

(To keep track of error propagation) we can interpret signals in

/ the presence of a fault as corresponding to a pair of 0/1 values

• f the form: v/vf

where where v =good (fault-free) value vf = the faulty value C

p it l i l (5 l d l i )

Composite logic values (5-valued logic): D = 1/0 D’ = 0/1 0 = 0/0 1 = 1/1 X = “unspecified” or “unknown”

Sharif University of Technology Testability: Lecture 9 Slide 37 of 45

D Algebra g

Signal value = pair v/vf or (v,vf) The set {(0,0),(0,1),(1,0),(1,1)} forms a Boolean algebra with

respect to the usual Boolean operators applied pair wise, so l B l t t th “D l b ” f we can apply Boolean operators to the “D-algebra” of symbols {0,1,D,D’,X}. F((u,uf),(v,vf)) = (F(u,v),F(uf,vf))

Sharif University of Technology Testability: Lecture 9 Page 38 of 41

F((u,uf),(v,vf)) (F(u,v),F(uf,vf))

Algebras: Roth’s 5-Valued and M th’ 9 V l d Muth’s 9-Valued

Symbol Meaning Good Machine Faulty Machine Symbol Meaning Good Machine Faulty Machine D 1/0 1 1 Roth’s D’ 0/1 1 Roths 0 Algebra 1 D 0/1 0/0 1 1/1 1 1 X 1 1/1 1 X X/X X / G0 0/X X G1 1/X 1 X Muth’s F0 X/0 X 0 additions F1 X/1 X 1

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Roth’s and Muth’s Higher-Order Roth s and Muth s Higher-Order Algebras

Represent two machines, which are simulated

simultaneously by a computer program:

t

Good circuit machine (1st value) Bad circuit machine (2nd value)

Better to represent both in the algebra: Better to represent both in the algebra:

Need only 1 pass of ATPG to solve both Good machine values that preclude bad machine values p become obvious sooner & vice versa

Needed for complete ATPG:

C bi ti l M lti th iti ti R th Al b Combinational: Multi-path sensitization, Roth Algebra Sequential: Muth Algebra -- good and bad machines may have different initial values due to fault

Sharif University of Technology Testability: Lecture 9 Slide 40 of 45

• 7. Fault-Independent Deterministic

Methods (Critical path method) Methods (Critical path method)

• References: Abramovici et al book [1990] Originally
• References: Abramovici et al. book [1990]. Originally

used in LASAR (Logic Automated Stimulus And Response) [Thomas 1971] Response) [Thomas 1971]

• A heuristic approach to generating tests for general

bi ti l l i t rk combinational logic networks.

• Single fault assumption.
• Main Features
• “Fault-independent” ATPG
• Derives tests for many faults without targeting specific faults
• Relies primarily on Justification procedure
• Values assigned to lines on sensitized paths are termed “critical”
• Values assigned to lines on sensitized paths are termed critical

Sharif University of Technology Testability: Lecture 9 Slide 41 of 45

Basic steps p

1. Select a PO and assign it a (critical) 0 or 1 value v. 2. Recursively justify v by assigning critical values to gate inputs y j y y g g g p wherever possible

Sharif University of Technology Testability: Lecture 9 Slide 42 of 45

Critical Path Method

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Pros and Cons of Critical Path Method Method

Advantages

g

Eliminates need for separate fault simulation step New tests can be quickly generated by modifying preceding tests

Disadvantages

Test generation steps tend to overlap causing unnecessary repetition Conflicts occur when justifying several paths. May have to replace critical patterns (cubes) by non-critical patterns c t ca patte s (cubes) by

• c t ca patte

s Does relatively unsystematic exploration of circuit paths Multiple-path sensitization is usually ignored, so some detectable f l b i d faults may be missed

Sharif University of Technology Testability: Lecture 9 Slide 44 of 45

Analog Fault Modeling Impractical for Logic ATPG

Huge # of different possible analog faults in

digital circuit digital circuit

Exponential complexity of ATPG algorithm – a

20 flip-flop circuit can take days of computing 20 flip flop circuit can take days of computing

Cannot afford to go to a lower-level model

Most test-pattern generators for digital circuits

p g g cannot even model at the transistor switch level

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