SLIDE 12
- H. Toyokawa @ JASRI/SPring-8
STD6, Carmal, CA 2006/9/15
PILATUS II
- A redesigned PILATUS-II readout
chip with 60 × 97 pixels in the UMC 0.25 µm COMS process has been developed to replace the PILATUS-II detector.
- Both of PILATUS I problems have
been overcome in the PILATUS-II chip.
- The yield of ‘good’ chips was
about 35% in the DMILL CMOS process, but even good chips still have around 5 % defective pixels. In the 0.25 mm COMS process,
- n the other hand, the yield of
perfect chips was more than 80%.
> 1 MHz < 10 kHz Countung Yield of chip / wafer Defect pixel / class 1 chip 2.4 ms 6.7 ms Readout time 100 MHz 10 MHz Digital clock 20 bit pseudo- random 15 bit pseudo- random Counter 6 bit DAC 4 bit DAC Threshold adjustment < 100 ns ~ 5 ms Analogue amp-
60 x 97 44 x 78 N of PIxel 172µm x 172 µm 217µm x 217 µm Pixel size UMC 0.25µm radiation tolerant CMOS process DMILL radiation tolerant CMOS process Process Pilatus-II Pilatus-I(SLS06) > 1 MHz < 10 kHz Countung Yield of chip / wafer Defect pixel / class 1 chip 2.4 ms 6.7 ms Readout time 100 MHz 10 MHz Digital clock 20 bit pseudo- random 15 bit pseudo- random Counter 6 bit DAC 4 bit DAC Threshold adjustment < 100 ns ~ 5 ms Analogue amp-
60 x 97 44 x 78 N of PIxel 172µm x 172 µm 217µm x 217 µm Pixel size UMC 0.25µm radiation tolerant CMOS process DMILL radiation tolerant CMOS process Process Pilatus-II Pilatus-I(SLS06) < 10 kHz Countung Yield of chip / wafer Defect pixel / class 1 chip 6.7 ms Readout time 10 MHz Digital clock 15 bit pseudo- random Counter 4 bit DAC Threshold adjustment ~ 5 ms Analogue amp-
44 x 78 N of PIxel 217µm x 217 µm Pixel size DMILL radiation tolerant CMOS process Process Pilatus-I(SLS06) < 10 kHz Countung Yield of chip / wafer Defect pixel / class 1 chip 6.7 ms Readout time 10 MHz Digital clock 15 bit pseudo- random Counter 4 bit DAC Threshold adjustment ~ 5 ms Analogue amp-
44 x 78 N of PIxel 217µm x 217 µm Pixel size DMILL radiation tolerant CMOS process Process Pilatus-I(SLS06) ~ 5 % ~ 30 % 0 % ~ 80 %