9.8m SPAD-based Analogue Single Photon Counting Pixel with Bias - - PowerPoint PPT Presentation

9.8μm SPAD-based Analogue Single Photon Counting Pixel with Bias Controlled Sensitivity

International Image Sensors Workshop Neale Dutton, Lindsay Grant and Robert Henderson

• SPAD
• SPAD +

Passive Quench

• Row and

Col Select

• Column

bus sharing

• Time Gate
• 1b Memory
• A “Jot”
• Time Gate
• Analogue

Counter or TAC

• Digital logic

in pixel

• TDC or

Digital Counters

Highest Fill Factor Lowest Fill Factor Least In- pixel Functionality Most In-pixel Functionality

CMOS SPAD Pixels

SPAD + Minimal Digital SPAD Only Analogue 1b Mem

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This Work

CMOS SPAD Pixels

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SPAD + Minimal Digital SPAD Only

[A] Richardson, J. et al. “A 32×32 50ps Resolution 10 bit Time to Digital Converter Array in 130nm CMOS for Time Correlated Imaging” 2009, CICC, Proc. Of, [B] Webster et al. "A silicon photomultiplier with >30% detection efficiency from 450-750nm and 11.6μm pitch NMOS-only pixel with 21.6% fill factor in 130nm

CMOS“ Proc of ESSDERC, 2012

[C] Walker, R. et al. “High Fill Factor Digital Silicon Photomultiplier Structures in 130nm CMOS Imaging Technology” 2012, IEEE NSS, Proc. Of, [D] Maruyama, Y. et al. “ A Time-Gated 128X128 CMOS SPAD Array for On-Chip Fluorescence Detection” IISW 2011

Analogue 1b Mem

9.8µm

Fabricated Test Array

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n+

N-well P-substrate

S T I S T I n+

Deep Retrograde N-well p+

S T I

N-well P-well P-well NMOS Logic

S T I

Pixel Schematic

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Column

RST RD GND VS VG EN DIS

VC

VDD VQ SPAD VHV SPADGND TEST DIS

M1 M2 M3 M4 M5 M6 M7 M8 M9 M10

SPAD & Quench Time Gate CTA Readout

VSPAD VIN VB MC CP

ΔVC = (ΔVIN– VB – VT_M7) . (CP/CMC)

Charge Transfer Amplifier Timing

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EN VSPAD VC

ΔVC

VB VIN

ΔVC = (ΔVIN– VB – VT_M7) . (CP/CMC)

RST

CTA Operation

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Bias Controllable Sensitivity VS = 0.0V VS = 0.3V VS = 0.9V VS = 0.6V

Pixel Characterisation

• Column Output Voltage Histogram – Discretised Poisson Curve

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1Ph 2Ph 3Ph 4Ph 5Ph 6Ph 7Ph

VS = 0.0V VS = 0.3V VS = 0.6V

Bias Controlled Sensitivity

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First Order Eq’n: ΔV = (ΔVIN– VB – VT) . (CP/CMC)

Full Well Capacity

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Pixel Response Non Uniformity

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𝜏∆𝑊 = 𝐷𝑄 𝐷𝑁𝐷 . 𝜏𝑊𝑈_𝑁7

2 + 𝜏𝑊𝑇𝑄𝐵𝐸 2

First Order Eqn:

Input Referred Noise

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[1] Teranishi 2012: Readount noise less than 0.3e- for electron counting

Switched Current Source Mode

• CTA operated as a switched current

source.

• This mode enables fast single photon

detection.

• Zero, one, few photons .
• Time gated QIS pixel, Fossum 2011 [11]

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Switched Current Source Mode

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Switched Current Source Mode

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Summary (1)

• 11T NMOS-only SPAD-based Single Photon Counting

pixel implemented in low voltage 130nm imaging CMOS with no extra implants.

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Summary (2)

• Two modes:
• ‘CTA’  Analogue Counting
• ‘SCS’  1b Memory
• Bias controlled sensitivity
• PRNU <2% for sensitivity range 5.5mV to 13.1mV/event
• Scalable pixel design with zero static bias current.

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Thank You Questions?