Testability Lecture 6: Logic Simulation Lecture 6: Logic Simulation - - PowerPoint PPT Presentation

Testability Lecture 6: Logic Simulation Lecture 6: Logic Simulation

Shaahin Hessabi Department of Computer Engineering Department of Computer Engineering Sharif University of Technology

Adapted from the presentation prepared by book authors

Slide 1 of 27

Outline Outline

Wh i i l i ?

• What is simulation?
• Circuit modeling
• True-value simulation algorithms

Compiled-code simulation

p

Event-driven simulation

• Summary
• Summary

Slide 2 of 27

Simulation

• Definition: Simulation refers to modeling of a design, its

function and performance.

• A software simulator is a computer program; an emulator is

a hardware simulator.

• Applications of simulation:
• Applications of simulation:

Verification Debugging Studying design alternative (cost/speed) Computing expected behavior for testing purposes

Sim lation for design erification:

• Simulation for design verification:

Validate assumptions Verify logic; e.g.,

y g ; g ,

independent of power-up state free of critical races & oscillation

Verify performance (timing)

Slide 3 of 27

Verify performance (timing)

Simulation Simulation

• Problems of simulation-based design verification

Tests are hand crafted A heuristic process that relies heavily on the designer’s intuition &

design knowledge

Not a precise procedure Very hard to prove that a test is complete Very hard to prove that a test is complete.

• Types of simulation:

Logic or switch level Timing Circuit Fault

Slide 4 of 27

Evaluating a Logic Simulator g g

• Attributes are accuracy, efficiency and generality
• Accuracy: close correspondence between the

predicted signal values & times, as calculated by the p g , y logic simulator and those occurring in the real circuit

• Efficiency: Simulators must be cost-effective

Efficiency: Simulators must be cost effective

• Generality: Should be able to handle a broad class of

circuits circuits

Synchronous, Asynchronous C

bi ti l S ti l

Combinational, Sequential Race/Hazard detection capabilities

Slide 5 of 27

Simulation for Verification Simulation for Verification

Specification S th i Design Response Synthesis Design Design (netlist) Response analysis Design changes True-value Computed True value simulation Input stimuli Computed responses

Slide 6 of 27 Sharif University of Technology Testability: Lecture 6

Modeling for Simulation g

• Modules, blocks or components described by

Input/output (I/O) function Delays associated with I/O signals Examples: binary adder, Boolean gates, FET, resistors and

capacitors

• Interconnects represent

ideal signal carriers, or ideal electrical conductors

• Netlist: a format (or language) that describes a design

( g g ) g as an interconnection of modules. Netlist may use hierarchy.

Slide 7 of 27

y

Example: A Full-Adder p

HA; c inputs: a, b;

• utputs: c, f;

AND: A1, (a, b), (c); a a c d d e e f f AND: A2, (d, e), (f); OR: O1, (a, b), (d); NOT: N1, (c), (e); b d d f f

HA HA

FA; inputs: A, B, C; t t C S

HA1 HA1

A D D Car Carry y

• utputs: Carry, Sum;

HA: HA1, (A, B), (D, E); HA: HA2, (E, C), (F, Sum); OR: O2 (D F) (Carry);

HA1 HA1 HA2 HA2

B B C C E F Sum Sum y OR: O2, (D, F), (Carry);

Slide 8 of 27 Sharif University of Technology Testability: Lecture 6

Signal States

• Two-states (0, 1) can be used for purely combinational logic

with zero-delay, and for synchronous circuits with a known initial state initial state.

• Three-states (0, 1, X) are essential for timing hazards and for

sequential logic initialization.

X (unknown state) represents:

Initial state of FFs and RAMs Interpreted as either 0 or 1

• Four-states (0, 1, X, Z) are essential for MOS devices.

Z (hold previous value)

• Analog signals are used for exact timing of digital logic and

for analog circuits.

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Information Loss of 3-Valued Logic g

3-value simulation symbolic simulation

• The three-state logic is pessimistic.
• Symbolic simulation can be effective if performed locally in a

Symbolic simulation can be effective if performed locally in a circuit.

impractical for large circuits.

Slide 10 of 27 Sharif University of Technology Testability: Lecture 6

Modeling Levels g

Circuit Signal Timing Modeling Application description Programming language-like HDL values 0, 1 Clock boundary level Function, behavior, RTL Architectural and functional verification Connectivity of Boolean gates, flip-flops and 0, 1, X and Z Zero-delay, unit-delay, multiple- , Logic verification Logic verification and test p p transistors Transistor size and connectivity, 0, 1, X and Z delay Zero-delay Switch Logic verification node capacitances Transistor technology data, connectivity, and Z Analog voltage Fine-grain timing Timing Timing verification node capacitances

• Tech. Data, active/

passive component vo ge Analog voltage, timing Continuous time Circuit Digital timing and analog circuit

Slide 11 of 27 Sharif University of Technology Testability: Lecture 6

p p connectivity voltage, current circuit verification

True-Value Simulation Algorithms

• True-Value refers to no fault in circuit
• Compiled-code simulation

Compiled code simulation

The compiled code is generated from an RTL or gate-level description

• f the circuit

Simulation is simply execution of the compiled code Applicable to zero-delay combinational logic

Timing cannot be properly modeled no hazard or signal propagation Timing cannot be properly modeled no hazard or signal propagation

is predicted

Also used for cycle-accurate synchronous sequential circuits for logic

ifi ti verification

Efficient for highly active circuits, but inefficient for low-activity circuits

Because time required to simulate a vector = t *N; where

q ;

– t = time required to simulate an element – N = number of elements

High-level (e g C language) models can be used

Slide 12 of 27

High-level (e.g., C language) models can be used

True-Value Simulation Algorithms (cont’d) g ( )

• Event-driven simulation
• Event driven simulation

Only gates or modules with input events are evaluated

(event means a signal change) (event means a signal change)

Delays can be accurately simulated for timing verification Efficient for low-activity circuits Efficient for low activity circuits The ratio of lines which change values to the total number of lines in

the circuit is called activity

Typically activity = 2 - 10 % Can be extended for fault simulation

Slide 13 of 27

Compiled-Code Algorithm p g

• Step 1: Levelize combinational logic and encode in a

il bl i l compilable programming language

Assign all PI lines level 0

Th l l f i L 1 ( L L L )

The level of a gate g is: Lg = 1 + max ( Li1 , Li2 , …Lin) Li1 , Li2 , …Lin are levels of inputs of gate g.

• Step 2: Initialize internal state variables (flip flops)
• Step 2: Initialize internal state variables (flip-flops)
• Step 3: For each input vector

S t

i i t i bl

Set primary input variables Repeat (until steady-state or max. iterations) Execute compiled code

Execute compiled code

– Elements are simulated in ascending order of logic level

Report or save computed variables

Slide 14 of 27

Compiled Simulation (Example)

• Given circuit C:

2

Generate code

• 2. Generate code

while(1) { Read_in ( a, b, c, d ) ; e = NAND ( a, b ) ; f = INV ( c ) ; g = NOR ( b f ) ;

1.

Levelize circuit

g = NOR ( b, f ) ; i = AND ( e, i ) ; j = NAND ( i, d );

• Level 0: a, b, c, d
• Level 1: e, f
• Level 2: g

Print ( e, i, j ) ; }

• Level 2: g
• Level 3: i
• Level 4: j

Slide 15 of 27 Sharif University of Technology Testability: Lecture 6

Event-Driven Algorithm g

Slide 16 of 27

Event-Driven Algorithm

(E h d li ) (Event scheduling)

Sc Scheduled heduled t Activity Activity li li

2 a =1 a =1 c =1 =1 e =1 e =1

t = t = 0 ev events c = c = 0 li list st d, e d, e

2 2 d d = 0 = 0 g =1 g =1

1 2 d 2 d = 1 1, e e = 0 f, f, g g

4 b = b =1 d d = 0 = 0 f = f =0

3 4 g = 0 = 0

stac stack g

5 6 g f f 1 1

Time Time Time, t Time, t

4 8

g

6 7 f f = 1 1 g

Slide 17 of 27 Sharif University of Technology Testability: Lecture 6

8 g 8 g = 1 1

Gate Evaluation - Input Scanning p g

• Assume only dealing with AND , OR , NAND, NOR

primiti e gates primitive gates

• These gates can be characterized by controlling value

c & inversion i c & inversion i I t O t t

c i

Inputs Output c x x c ⊕ i

c i AND OR 1

x c x c ⊕ i x x c c ⊕ i

NAND 1 NOR 1 1

x x c c ⊕ i c’ c’ c’ c’ ⊕ i

Slide 18 of 27 Sharif University of Technology Testability: Lecture 6

Delay Types

• Transport (propagation) delay: time interval

between the generation of a signal transition at a g g gate output (source) and its arrival at the input of a fanout gate

transition independent transition dependent : rise/fall delays specified separately

• Inertial (switching) delay: time interval between an

input change and the output change of a gate.

Slide 19 of 27

Logic Model of MOS Circuit Logic Model of MOS Circuit

VD VD

D

pMOS FETs

Dc Da c a Ca

a

C a c c

c

b Db Cc Cb

b

b

nMOS

Da and Db are interconnect or ti d l

FETs

propagation delays D is inertial or Ca , Cb and Cc are parasitic capacitances Dc is inertial or switching delay

• f gate

Slide 20 of 27 Sharif University of Technology Testability: Lecture 6

Switching Delay Models

• Zero delay: Output changes instantly in response to

an input p

useful for logic simulation of combinational circuits

• Unit delay: All gates have one unit delay, no delay

y g y, y for interconnects

circuits with feedback can also be simulated

• Multiple delay: delays are modeled as multiples of

some time unit

Each gate is assigned a rise delay (dr) and a fall delay (df)

• Ambiguous delay or Minmax delay

Slide 21 of 27

Options for Inertial Delay Options for Inertial Delay

(simulation of a NAND gate) Transient

b b a

Inputs region

c c (CMOS) (CMOS) c c (z (zer ero delay delay) ( i ( it d d l )

ation

c (un unit d it delay ay) c c (m (multiple ultiple delay delay)

ic simula

rise= rise=5, fall=3 , fall=3

Ti it

c c (minm (minmax delay) delay)

Logi

min =2, max =5 min =2, max =5 Unkno Unknow n (X n (X)

Slide 22 of 27 Sharif University of Technology Testability: Lecture 6

Time units 5

Event-Driven Simulation with Delay

Need a “time-flow” mechanism

Slide 23 of 27 Sharif University of Technology Testability: Lecture 6

Time Flow Mechanism & Event Scheduling

• When an element i is simulated and it is determined

h i i l j h h d i that its output signal j has changed state; i.e., Vnew(j) ≠ Vold(j), then signal j must be scheduled to h V (j) i t Δi change to Vnew(j) at time t+ Δi

where t : the current simulation time Δi : the delay of element i Δi : the delay of element i

The event ( j, Vnew ( j), t+ Δi ) is scheduled to occur in th f t r in the future.

• Need an event queue for each time of simulation

Slide 24 of 27

Time Wheel (Circular Stack) Time Wheel (Circular Stack)

t=0 t=0 max max Cur Current ent time time 1 2 pointer pointer Ev Event link-list ent link-list 3 4 5 6 7

Slide 25 of 27 Sharif University of Technology Testability: Lecture 6

Efficiency of Event-driven Simulator y

• Simulates events (value changes) only
• Speed up over compiled-code can be ten times or

more; in large logic circuits about 0.1 to 10% gates become active for an input change

Lar Large lo logic gic bloc block w ithout k w ithout activity activity Stead Steady 0 0 to 1 e 0 to 1 event ent Stead Steady 0 (no e (no event) ent) activity activity 0 to 1 e 0 to 1 event ent

Slide 26 of 27

Summary

• Logic or true-value simulators are essential tools for

design verification.

• Verification vectors and expected responses are

generated (often manually) from specifications.

• A logic simulator can be implemented using either

g p g compiled-code or event-driven method.

• Per vector complexity of a logic simulator is
• Per vector complexity of a logic simulator is

approximately linear in circuit size.

• Modeling level determines the evaluation
• Modeling level determines the evaluation

procedures used in the simulator.

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