Testability Lecture 6: Logic Simulation Lecture 6: Logic Simulation - PowerPoint PPT Presentation

Testability Lecture 6: Logic Simulation Lecture 6: Logic Simulation Shaahin Hessabi Department of Computer Engineering Department of Computer Engineering Sharif University of Technology Adapted from the presentation prepared by book authors Slide 1 of 27

Outline Outline • What is simulation? Wh i i l i ? • Circuit modeling • True-value simulation algorithms � Compiled-code simulation p � Event-driven simulation • Summary • Summary Slide 2 of 27

Simulation • Definition: Simulation refers to modeling of a design, its function and performance. • A software simulator is a computer program; an emulator is a hardware simulator. • Applications of simulation: • Applications of simulation: � Verification � Debugging � Studying design alternative (cost/speed) � Computing expected behavior for testing purposes • Simulation for design verification: Sim lation for design erification: � Validate assumptions � Verify logic; e.g., y g ; g , � independent of power-up state � free of critical races & oscillation � Verify performance (timing) � Verify performance (timing) Slide 3 of 27

Simulation Simulation • Problems of simulation-based design verification � Tests are hand crafted � A heuristic process that relies heavily on the designer’s intuition & design knowledge � Not a precise procedure � Very hard to prove that a test is complete � Very hard to prove that a test is complete. • Types of simulation: � Logic or switch level � Timing � Circuit � Fault Slide 4 of 27

Evaluating a Logic Simulator g g • Attributes are accuracy , efficiency and generality • Accuracy: close correspondence between the predicted signal values & times, as calculated by the p g , y logic simulator and those occurring in the real circuit • Efficiency: Simulators must be cost-effective Efficiency: Simulators must be cost effective • Generality: Should be able to handle a broad class of circuits circuits � Synchronous, Asynchronous � C � Combinational, Sequential bi ti l S ti l � Race/Hazard detection capabilities Slide 5 of 27

Simulation for Verification Simulation for Verification Specification S Synthesis th i Response Response Design Design Design Design analysis changes (netlist) Computed Computed True-value True value Input stimuli responses simulation Slide 6 of 27 Sharif University of Technology Testability: Lecture 6

Modeling for Simulation g • Modules, blocks or components described by � Input/output (I/O) function � Delays associated with I/O signals � Examples: binary adder, Boolean gates, FET, resistors and capacitors • Interconnects represent � ideal signal carriers, or � ideal electrical conductors • Netlist: a format (or language) that describes a design ( g g ) g as an interconnection of modules. Netlist may use hierarchy. y Slide 7 of 27

Example: A Full-Adder p HA; c c inputs: a, b; a a outputs: c, f; e e AND: A1, (a, b), (c); d d d d f f f f AND: A2, (d, e), (f); b HA HA OR: O1, (a, b), (d); NOT: N1, (c), (e); FA; D D inputs: A, B, C; A Carry Car y y HA1 HA1 HA1 HA1 outputs: Carry, Sum; t t C S F E B B HA: HA1, (A, B), (D, E); HA2 HA2 Sum Sum C C HA: HA2, (E, C), (F, Sum); OR: O2 (D F) (Carry); OR: O2, (D, F), (Carry); Slide 8 of 27 Sharif University of Technology Testability: Lecture 6

Signal States • Two-states (0, 1) can be used for purely combinational logic with zero-delay, and for synchronous circuits with a known initial state initial state. • Three-states (0, 1, X) are essential for timing hazards and for sequential logic initialization. � X (unknown state) represents: � Initial state of FFs and RAMs � Interpreted as either 0 or 1 • Four-states (0, 1, X, Z) are essential for MOS devices. Z (hold previous value) 0 0 0 • Analog signals are used for exact timing of digital logic and for analog circuits. Slide 9 of 27

Information Loss of 3-Valued Logic g 3-value simulation symbolic simulation • The three-state logic is pessimistic. • Symbolic simulation can be effective if performed locally in a Symbolic simulation can be effective if performed locally in a circuit. � impractical for large circuits. Slide 10 of 27 Sharif University of Technology Testability: Lecture 6

Modeling Levels g Application Modeling Signal Timing Circuit level description values Architectural Programming Clock 0, 1 Function, and functional boundary language-like HDL behavior, RTL , verification verification Connectivity of Zero-delay, Logic Logic 0, 1, X verification unit-delay, Boolean gates, and Z multiple- flip-flops and p p and test delay transistors Transistor size Logic Switch 0, 1, X Zero-delay and connectivity, verification and Z and Z node capacitances Transistor technology Timing Fine-grain Timing Analog data, connectivity, verification vo voltage ge timing timing node capacitances Digital timing Continuous Circuit Tech. Data, active/ Analog and analog time passive component p p voltage, voltage, circuit circuit connectivity current verification Slide 11 of 27 Sharif University of Technology Testability: Lecture 6

True-Value Simulation Algorithms • True-Value refers to no fault in circuit • Compiled-code simulation Compiled code simulation � The compiled code is generated from an RTL or gate-level description of the circuit � Simulation is simply execution of the compiled code � Applicable to zero-delay combinational logic � � Timing cannot be properly modeled � no hazard or signal propagation � � Timing cannot be properly modeled � no hazard or signal propagation is predicted � Also used for cycle-accurate synchronous sequential circuits for logic verification ifi ti � Efficient for highly active circuits, but inefficient for low-activity circuits � Because time required to simulate a vector = t *N; where q ; – t = time required to simulate an element – N = number of elements � High-level (e g C language) models can be used � High-level (e.g., C language) models can be used Slide 12 of 27

True-Value Simulation Algorithms (cont’d) g ( ) • Event-driven simulation • Event driven simulation � Only gates or modules with input events are evaluated ( event means a signal change ) ( event means a signal change ) � Delays can be accurately simulated for timing verification � Efficient for low-activity circuits � Efficient for low activity circuits � The ratio of lines which change values to the total number of lines in the circuit is called activity � Typically activity = 2 - 10 % � Can be extended for fault simulation Slide 13 of 27

Compiled-Code Algorithm p g • Step 1: Levelize combinational logic and encode in a compilable programming language il bl i l � Assign all PI lines level 0 � The level of a gate g is: Lg = 1 + max ( L i1 , L i2 , …L in ) Th l l f i L 1 ( L L L ) � L i1 , L i2 , …L in are levels of inputs of gate g. • Step 2: Initialize internal state variables (flip flops) • Step 2: Initialize internal state variables (flip-flops) • Step 3: For each input vector � Set primary input variables � S t i i t i bl � Repeat (until steady-state or max. iterations) � Execute compiled code Execute compiled code – Elements are simulated in ascending order of logic level � Report or save computed variables Slide 14 of 27

Compiled Simulation (Example) • Given circuit C: 2. Generate code Generate code 2 while(1) { Read_in ( a, b, c, d ) ; e = NAND ( a, b ) ; f = INV ( c ) ; Levelize circuit 1. g = NOR ( b f ) ; g = NOR ( b, f ) ; � Level 0: a, b, c, d i = AND ( e, i ) ; � Level 1: e, f j = NAND ( i, d ); � � Level 2: g Level 2: g Print ( e, i, j ) ; � Level 3: i } � Level 4: j Slide 15 of 27 Sharif University of Technology Testability: Lecture 6

Event-Driven Algorithm g Slide 16 of 27

Event-Driven Algorithm (Event scheduling) (E h d li ) Sc Scheduled heduled Activity Activity events ev t li list li li st a =1 a =1 e =1 e =1 t = 0 t = 0 c = c = 0 0 d, e d, e 2 c =1 =1 0 1 g =1 g =1 2 2 2 2 d = 1 d 1, e e = 0 0 f, f, g g d = 0 d d = 0 d = 0 = 0 stack 3 stac 4 f =0 f = b =1 b = 4 g = 0 g = 0 Time Time 5 g g 6 6 f = 1 f f f 1 1 1 g 8 0 4 Time, t Time, t 7 8 8 g g = 1 1 Slide 17 of 27 Sharif University of Technology Testability: Lecture 6

Gate Evaluation - Input Scanning p g • Assume only dealing with AND , OR , NAND, NOR primiti e gates primitive gates • These gates can be characterized by controlling value c & inversion i c & inversion i c c i i Inputs I t O t Output t AND 0 0 c ⊕ i c x x OR 1 0 NAND 0 1 c ⊕ i x c x NOR 1 1 c ⊕ i c ⊕ i x x x x c c c’ ⊕ i c’ c’ c’ Slide 18 of 27 Sharif University of Technology Testability: Lecture 6

Delay Types • Transport (propagation) delay: time interval between the generation of a signal transition at a g g gate output (source) and its arrival at the input of a fanout gate � transition independent � transition dependent : rise/fall delays specified separately • Inertial (switching) delay: time interval between an input change and the output change of a gate. Slide 19 of 27