Motivation Power and energy: Will not motivate low power topic - PDF document

Motivation Power and energy: • Will not motivate low power topic … • You are here, aren’t you!? how low can we go? Lars Svensson • Scaling and limits set the context for larssv@chalmers.se insights and for good competitive design • … and there is an intellectual challenge too, of course :-) 1 2 Overview / Outline • Will start from a CMOS perspective • Gradually, circuits and examples will become less and less like the ordinary CMOS energetics gates • Practical design methods in later lectures (Per Larsson-Edefors) • End at fundamental physical limit 3 4 CMOS inverter CMOS inverter • Half of injected energy V dd V dd • Input goes low, output is dissipated during charge, charged Q other half during discharge Q • Q = C L V dd • E cycle = E inj C L C L • E inj = V dd · Q = C L V dd2 • Repeat with frequency f: • E diss = V avg · Q = C L V dd2 / 2 • P = f C L V dd2 = ß f ck C L V dd2 • E CL = E inj – E diss = C L V dd2 / 2 • Several capacitive nodes: • Dissipated during discharge • P = f ck V dd2 ! (ß i C Li ) 5 6

How reduce E and P? V dd reduction • Gate-source voltage V GS of device is • Reduce f, C, and/or V reduced too • V looks especially promising since squared V dd • Drain current reduced • Reduce swing wrt V dd Q • I d ~ (V dd – V T ) x , 1 < x " 2 • One-time gain, but OK • Time to charge C L : C L • Used in memories, I/O • t ~ Q / I d ~ # V dd C L / (V dd – V T ) x • Logic typically full-swing • Goes toward +inf as V dd approaches • Reduce V dd threshold voltage V T 7 8 Further V dd reduction Leakage currents • To avoid speed reduction, V T must be reduced too • Keep V dd / (V dd – V T ) x approx. constant • Reduce V T as fast as V dd • Devices will conduct even below V T • How far? • Causes leakage power when idle • Exponential increase with lower V T will eventually defeat any switching power gain 9 10 Optimal voltages Optimal choice? • Sakurai surfaces of power and delay • Minimum moves with activity factor ß • Same delay at A and B, but lower • Weighted sum of active and idle powers power at B 11 12

Metrics Energy-delay curves Delay vs energy when Vdd/Vt is varied 10 • Sakurai minimum steers towards low 9 8 performance! 7 6 Delay • Does not care about time 5 4 3 • Other metrics of frugality? 2 1 • Power = Energy per time 0 0 2 4 6 8 10 12 14 16 Energy • Energy • General way of relating energy and delay for a design • EDP = Energy * time • Useful to invert one axis 13 14 Fast processing with Energy-delay curves slow circuits? Delay vs energy when Vdd/Vt is varied Inverse delay vs energy when Vdd/Vt is varied 10 1.4 • Energy per operation falls faster than 9 1.2 performance with reduced V dd 8 1 7 Inverse delay 6 0.8 • Opportunity! Delay 5 0.6 4 3 • Reduce V dd until performance is halved, 0.4 2 0.2 then duplicate hardware 1 0 0 0 2 4 6 8 10 12 14 16 0 2 4 6 8 10 12 14 16 Energy Energy • Examples: pipelining, parallel processing, • General way of relating energy and delay multicore for a design • Overheads • Useful to invert one axis 14 15 !"#$%&'#$()*+&,-+#)*./01$2+#3 !"#$%&'#$()*+&,-+#)*./01$2+#3 :'(;*.*4,'* :'(;*.*4,'* <='%7.= <='%7.= 08 08 #6 #6 01>3%&/45(6%7(4( 01>3%&/45(6%7(4( !6 %6 %6 !6 %&$' &!%' &!%' 08 1 "#$%&''()*%%%%%%%"#$%+,-./%0123%&/45(6%7(4( "#$%&''()*%%%%%%%"#$%+,-./%0123%&/45(6%7(4( %&$' !%)' !%)' 405/*12 , 405/*12 , 0123%<',A=/4.,; 08 B 0123%<',A=/4.,; $#' $#' 3 # -./0*12 3 -./0*12 � " "=@,') =@,') !$' !$' � Moore / Dennard 3 !!! 08 2 #' #' -./0*12 3 -./0*12 !!! � "./',C',/=**,' � "./',C',/=**,' 3 44 -./0*12 3 -./0*12 44 !' !' 08 > -./0*12 3 -./0*12 3 %&$" %&$" *#)$, *#)$, $#" $#" scaling 08 3 *+)$, )(%)$ *+)$, )(%)$ #" #" !$" !$" 08 D )()$ )()$ !" !" )()( )()( 08 9 #((# #((# 08 E 08 0 08 8 01>8 01>8 01>3 01>3 0128 0128 0123 0123 01B8 01B8 01B3 01B3 0118 0118 0113 0113 E888 E888 E883 E883 E808 E808 $,5'/=?%!;4=6% $,5'/=?%!;4=6% 16 17

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Scaling limit? Scaling limit? 22 nm • Carver Mead’s 1994 predictions • Carver Mead’s 1994 predictions 21 21 Limits Limits 22 22 Limits Oxide thickness • Single atom layers! • Scaling cannot go much further… 22 23

Charging C L • Charging + discharging C L to V dd costs C L V dd2 , always. Right? • No. Energetics revisited C L Q • Replace V dd with ramp! • 0 V dd • Same charge transferred • … but V avg may be < V dd / 2 24 25 Charging C L E diss < C L V dd2 / 2 • Charging + discharging C L to V dd costs C L V dd2 , always. • But how big is it? C L Right? Q • Model switch device as resistor R • No. • Then, if ramp duration is T C L Q • Replace V dd with ramp! • I = Q / T = C L V dd / T • 0 V dd • P = I 2 R = (RC L / T) C L V dd2 / T E diss < C L V dd2 / 2 • Same charge transferred • E diss = P · T = (RC L / T) C L V dd2 • … but V avg may be < V dd / 2 25 26 E diss < C L V dd2 / 2 E diss < C L V dd2 / 2 • But how big is it? • But how big is it? C L C L Q Q • Model switch device as resistor R • Model switch device as resistor R • Then, if ramp duration is T • Then, if ramp duration is T 2 RC L < T • I = Q / T = C L V dd / T • I = Q / T = C L V dd / T • P = I 2 R = (RC L / T) C L V dd2 / T • P = I 2 R = (RC L / T) C L V dd2 / T • E diss = P · T = (RC L / T) C L V dd2 • E diss = P · T = (RC L / T) C L V dd2 26 26

Observations E diss < C L V dd2 / 2 E diss = (RC L / T) C L V dd2 • But how big is it? C L Q • It is good for R to be small • Model switch device as resistor R • R does not matter for power in • Then, if ramp duration is T 2 RC L < T “standard” charging • I = Q / T = C L V dd / T 2 / V dd2 • E diss arbitrarily small for large T • P = I 2 R = (RC L / T) C L V dd2 / T C L < • “Adiabatic charging” • E diss = P · T = (RC L / T) C L V dd2 E diss • No heat delivered to environment 26 27 Observations How size the switch? E diss = (RC L / T) C L V dd2 • Small R is good! • … but requires a wide transistor … • It is good for R to be small • … which means a large gate • R does not matter for power in capacitance … “standard” charging • … which is expensive to charge / • E diss arbitrarily small for large T discharge • “Adiabatic charging” y r • To reap benefits, must charge and e v o c • No heat delivered to environment e discharge gate capacitance adiabatically r t a e h o N 27 28 How size the switch? Yes. The discharge. • Small R is good! • To adiabatically charge and discharge a capacitance, the controlling device must be on • … but requires a wide transistor … throughout • … which means a large gate • … so its gate must be charged before and capacitance … discharged after the load … • … which is expensive to charge / discharge etc… • To reap benefits, must charge and discharge gate capacitance adiabatically C L 28 29