Sequential Circuit ATPG Ti Time-Frame Expansion F E i - PowerPoint PPT Presentation

Digital Testing: Lecture 13 Sequential Circuit ATPG Ti Time-Frame Expansion F E i Instructor: Shaahin Hessabi Department of Computer Engineering Sharif University of Technology Sharif University of Technology Adapted from lecture notes prepared by the book authors

Contents � Problem of sequential circuit ATPG � Time-frame expansion � Nine-valued logic � ATPG implementation and drivability ATPG i l t ti d d i bilit � Complexity of ATPG � Cycle-free and cyclic circuits � Cycle free and cyclic circuits � Summary Lecture 13: Sequential ATPG Sharif University of Technology Slide 2 of 19

Sequential Circuits q � A sequential circuit has memory in addition to combinational logic. � Test for a fault in a sequential circuit is a sequence of vectors, which: � Initializes the circuit to a known state I i i li h i i k � Activates the fault, and � Propagates the fault effect to a primary output � Propagates the fault effect to a primary output � Methods of sequential circuit ATPG � Time-frame expansion methods p � Simulation-based methods Lecture 13: Sequential ATPG Sharif University of Technology Slide 3 of 19

Example: A Serial Adder p A n B n 1 1 s-a-0 D D 1 1 D X C n C n C n+1 X 1 1 Combinational logic C bi ti l l i S n X FF Lecture 13: Sequential ATPG Sharif University of Technology Slide 4 of 19

Time-Frame Expansion p A n-1 B n-1 A n B n Time-frame -1 Time-frame 0 1 1 1 1 s-a-0 s-a-0 D X X D D D D 1 1 D 1 C n-1 X D 1 C n 1 C C n+1 n 1 X 1 Combinational logic Combinational logic 1 S S n-1 S n X D FF Lecture 13: Sequential ATPG Sharif University of Technology Slide 5 of 19

Concept of Time-Frames p � If the test sequence for a single stuck-at fault contains n vectors: vectors: � Replicate combinational logic block n times � Place fault in each block � Place fault in each block � Generate a test for the multiple stuck-at fault using combinational ATPG with 9-valued logic Vector - n +1 Vector -1 Vector 0 Fault Unknow n Next State Time- Time- Time- or given or given state t t variables i bl frame frame frame Init. state 0 - n +1 -1 Comb. block PO - n +1 PO -1 PO 0 Lecture 13: Sequential ATPG Sharif University of Technology Slide 6 of 19

E Example for Logic Systems mple for Lo ic S stems FF1 B A FF2 s-a-1 s-a-1 Lecture 13: Sequential ATPG Sharif University of Technology Slide 7 of 19

Five-Valued Logic (Roth) g ( ) 0,1, D, D, X A 0 A 0 s-a-1 s-a-1 D D X X X FF1 FF1 FF1 X D D FF2 FF2 B X B X Time-frame -1 Time frame 1 Time-frame 0 Time frame 0 Lecture 13: Sequential ATPG Sharif University of Technology Slide 8 of 19

Nine-Valued Logic (Muth) g ( ) 0,1, 1/0, 0/1, 1/ X, 0/ X , X/ 0, X/ 1, X A 0 A X s-a-1 s-a-1 X /1 0/1 0/ X X 0/ X FF1 FF1 FF1 0/1 X X /1 FF2 FF2 B X B 0/1 Time-frame -1 Time frame 1 Time-frame 0 Time frame 0 Lecture 13: Sequential ATPG Sharif University of Technology Slide 9 of 19

Implementation of ATPG p � Select a PO for fault detection based on drivability analysis. � Place a logic value, 1/0 or 0/1, depending on fault type and Pl l i l 1/0 0/1 d di f l d number of inversions. � Justify the output value from PIs, considering all necessary � Justify the output value from PIs considering all necessary paths and adding backward time-frames. � If justification is impossible then use drivability to select � If justification is impossible, then use drivability to select another PO and repeat justification. � If the procedure fails for all reachable POs, then the fault is � If the procedure fails for all reachable POs, then the fault is untestable. � If 1/0 or 0/1 cannot be justified at any PO, but 1/X or 0/X j y , can be justified, then the fault is potentially detectable. Lecture 13: Sequential ATPG Sharif University of Technology Slide 10 of 19

Drivability Example y p (11, 16) (22, 17) (10, 15) (10, 16) d(0/1) = ( ) 8 s-a-1 1 d(0/1) = 4 d(1/0) = 32 d(0/1) = 8 d(1/0) = 8 d(1/0) = 20 (5, 9) ( , (4, 4) ) (17, 11) d(0/1) = 9 (6, 10) (CC0, CC1) d(0/1) = 120 d(1/0) = FF 8 = (6, 4) d(1/0) = 27 d(0/1) = 109 d(0/1) 109 d(1/0) = 8 CC0 and CC1 are SCOAP combinational controllabilities CC0 and CC1 are SCOAP combinational controllabilities d(0/1) and d(1/0) of a line are effort measures for driving a specific fault effect to that line Lecture 13: Sequential ATPG Sharif University of Technology Slide 11 of 19

Complexity of ATPG p y � Synchronous circuit -- All flip-flops controlled by clocks; PI and PO synchronized with clock: � Cycle-free circuit – No feedback among flip-flops: Test generation for a fault needs no more than dseq + 1 time-frames where dseq is the for a fault needs no more than dseq + 1 time-frames, where dseq is the sequential depth. � Cyclic circuit – Contains feedback among flip-flops: May need 9 Nff time-frames, where Nff is the number of flip-flops. f h h b f fl fl � Asynchronous circuit – Higher complexity! Smax Time- Time- Time- Time- Time- S2 S3 S1 S0 Frame Frame Frame Frame Frame max 1 max-1 max-2 max 2 -2 -2 -1 -1 0 0 max = Number of distinct vectors w ith 9-valued elements = 9 Nff Lecture 13: Sequential ATPG Sharif University of Technology Slide 12 of 19

Cycle-Free Circuits y � Characterized by absence of cycles among flip-flops, and a sequential depth, dseq . � dseq is the maximum number of flip-flops on any path d i h i b f fli fl h between PI and PO. � Both good and faulty circuits are initializable � Both good and faulty circuits are initializable. � Test sequence length for a fault is bounded by dseq + 1. Lecture 13: Sequential ATPG Sharif University of Technology Slide 13 of 19

Cycle-Free Example y p Circuit Circuit F2 2 F3 F3 F1 3 Level = 1 F2 2 s - graph F3 F3 F1 F1 d dseq = 3 3 3 Level = 1 All faults are testable See Example 8 6 All faults are testable. See Example 8.6. Lecture 13: Sequential ATPG Sharif University of Technology Slide 14 of 19

Cyclic Circuit Example y p Modulo-3 counter Modulo-3 counter Z CNT CNT F2 F1 s - graph F2 F1 Lecture 13: Sequential ATPG Sharif University of Technology Slide 15 of 19

Modulo-3 Counter � Cyclic structure – Sequential depth is undefined. � Circuit is not initializable. No tests can be generated for any stuck-at fault. � After expanding the circuit to 9 Nff = 81, or fewer, time-frames it t 9 Nff � Aft di th i 81 f ti f ATPG program calls any given target fault untestable. � Circuit can only be functionally tested by multiple � Circuit can only be functionally tested by multiple observations. � Functional tests, when simulated, give no fault coverage. Lecture 13: Sequential ATPG Sharif University of Technology Slide 16 of 19

Adding Initializing Hardware Adding Initializing Hardware Initializable modulo-3 counter Initializable modulo-3 counter Z CNT CNT F2 F1 s-a-0 s-a-1 CLR s-a-1 s-a-1 Untestable fault Potentially detectable fault s - graph F2 F1 Lecture 13: Sequential ATPG Sharif University of Technology Slide 17 of 19

Benchmark Circuits Circuit s1494 s1196 s1238 s1488 PI 14 14 8 8 PO 14 14 19 19 FF 18 18 6 6 Gates 508 647 529 653 Structure Cyclic Cycle-free Cycle-free Cyclic Seq depth Seq. depth 4 4 4 4 -- -- Total faults 1242 1355 1486 1506 Detected faults 1239 1283 1384 1379 Potentially detected faults 0 2 0 2 Untestable faults 30 3 72 26 Abandoned faults 0 0 76 97 Fault coverage (%) 99.8 94.7 93.1 91.6 Fault efficiency (%) Fault efficiency (%) 100 0 100.0 100.0 100 0 94 8 94.8 93 4 93.4 Max. sequence length 3 28 3 24 Total test vectors 559 313 308 525 Gentest CPU s (Sparc 2) 10 15 19941 19183 Lecture 13: Sequential ATPG Sharif University of Technology Slide 18 of 19

Summary � Combinational ATPG algorithms are extended: � Time-frame expansion unrolls time as combinational array � Nine-valued logic system � Justification via backward time � Cycle-free circuits: � Cycle free circuits: � Require at most dseq time-frames � Always initializable � Cyclic circuits: � May need 9 Nff time-frames � Circuit must be initializable � Partial scan can make circuit cycle-free (Chapter 14) � Asynchronous circuits: � High complexity � Low coverage and unreliable tests � Simulation-based methods are more useful (Section 8.3) ( ) Lecture 13: Sequential ATPG Sharif University of Technology Slide 19 of 19