Sequential Circuit ATPG Ti Time-Frame Expansion F E i - - PowerPoint PPT Presentation

Digital Testing: Lecture 13

Sequential Circuit ATPG Ti F E i Time-Frame Expansion

Instructor: Shaahin Hessabi Department of Computer Engineering Sharif University of Technology Sharif University of Technology Adapted from lecture notes prepared by the book authors

Contents

Problem of sequential circuit ATPG Time-frame expansion

Nine-valued logic

ATPG i l t ti d d i bilit

ATPG implementation and drivability Complexity of ATPG Cycle-free and cyclic circuits Cycle free and cyclic circuits

Summary

Sharif University of Technology Lecture 13: Sequential ATPG Slide 2 of 19

Sequential Circuits q

A sequential circuit has memory in addition to

combinational logic.

Test for a fault in a sequential circuit is a sequence of

vectors, which:

I i i li h i i k

Initializes the circuit to a known state Activates the fault, and Propagates the fault effect to a primary output Propagates the fault effect to a primary output

Methods of sequential circuit ATPG

Time-frame expansion methods

p

Simulation-based methods

Sharif University of Technology Lecture 13: Sequential ATPG Slide 3 of 19

Example: A Serial Adder p

An Bn s-a-0 1 1 D 1 D Cn 1 X D Cn Cn+1 1 X C bi ti l l i FF Sn 1 X Combinational logic

Sharif University of Technology Lecture 13: Sequential ATPG Slide 4 of 19

Time-Frame Expansion p

An Bn

X s-a-0 1 1 D s-a-0 1 1 D D

An-1 Bn-1

Time-frame -1 Time-frame 0

Cn C

1

1 X 1 1 D D 1 1 X D

Cn-1

D

n

Cn+1

X Combinational logic

S

Combinational logic 1 1

Sn Sn-1

D X

FF

Sharif University of Technology Lecture 13: Sequential ATPG Slide 5 of 19

Concept of Time-Frames p

If the test sequence for a single stuck-at fault contains n

vectors: vectors:

Replicate combinational logic block n times Place fault in each block Place fault in each block Generate a test for the multiple stuck-at fault using combinational

ATPG with 9-valued logic Fault

Vector 0 Vector -1 Vector -n+1 Time- Time- Time- Unknow n

• r given

State i bl Next t t

Comb.

frame frame

• 1

frame

• n+1
• r given
• Init. state

variables state

Sharif University of Technology Lecture 13: Sequential ATPG

block

PO 0 PO -1 PO -n+1

Slide 6 of 19

E mple for Lo ic S stems Example for Logic Systems

FF1 B FF2 A s-a-1 s-a-1

Sharif University of Technology Lecture 13: Sequential ATPG Slide 7 of 19

Five-Valued Logic (Roth) g ( ) 0,1, D, D, X

A s-a-1 A s-a-1 X D X X D FF1 FF1 X FF1 FF2 FF2 D D B X B X Time-frame -1 Time-frame 0

Sharif University of Technology Lecture 13: Sequential ATPG

Time frame 1 Time frame 0

Slide 8 of 19

Nine-Valued Logic (Muth) g ( )

0,1, 1/0, 0/1, 1/X, 0/X, X/0, X/1, X

A s-a-1 A X s-a-1 X 0/1 0/X 0/X X/1 FF1 FF1 X FF1 FF2 FF2 0/1 X/1 B X B 0/1 Time-frame -1 Time-frame 0

Sharif University of Technology Lecture 13: Sequential ATPG

Time frame 1 Time frame 0

Slide 9 of 19

Implementation of ATPG p

Select a PO for fault detection based on drivability analysis.

Pl l i l 1/0 0/1 d di f l d

Place a logic value, 1/0 or 0/1, depending on fault type and

number of inversions.

Justify the output value from PIs considering all necessary Justify the output value from PIs, considering all necessary

paths and adding backward time-frames.

If justification is impossible then use drivability to select If justification is impossible, then use drivability to select

another PO and repeat justification.

If the procedure fails for all reachable POs, then the fault is If the procedure fails for all reachable POs, then the fault is

untestable.

If 1/0 or 0/1 cannot be justified at any PO, but 1/X or 0/X

j y , can be justified, then the fault is potentially detectable.

Sharif University of Technology Lecture 13: Sequential ATPG Slide 10 of 19

Drivability Example y p

1 (10, 15) (11, 16) (10, 16) (22, 17) d(0/1) = 8 d(0/1) = 4 d(1/0) = s-a-1 (4, 4) (5, 9) ( ) d(1/0) = 32 8 d(0/1) = d(1/0) = 20 8 (CC0, CC1) = (6, 4) ( , ) (17, 11) d(0/1) = 9 d(1/0) = d(0/1) = 109 d(0/1) = 120 d(1/0) = 27 (6, 10) 8 FF d(0/1) 109 d(1/0) = 8 CC0 and CC1 are SCOAP combinational controllabilities CC0 and CC1 are SCOAP combinational controllabilities d(0/1) and d(1/0) of a line are effort measures for driving a specific fault effect to that line

Sharif University of Technology Lecture 13: Sequential ATPG Slide 11 of 19

Complexity of ATPG p y

Synchronous circuit -- All flip-flops controlled by

clocks; PI and PO synchronized with clock:

Cycle-free circuit – No feedback among flip-flops: Test generation

for a fault needs no more than dseq + 1 time-frames where dseq is the for a fault needs no more than dseq + 1 time-frames, where dseq is the sequential depth.

Cyclic circuit – Contains feedback among flip-flops: May need 9Nff

f h h b f fl fl time-frames, where Nff is the number of flip-flops.

Asynchronous circuit – Higher complexity!

Time- Frame Time- Frame max-1 Time- Frame max-2 Time- Frame

• 2

Time- Frame

• 1

S0 S1 S2 S3 Smax max 1 max 2

• 2
• 1

max = Number of distinct vectors w ith 9-valued elements = 9 Nff

Sharif University of Technology Lecture 13: Sequential ATPG Slide 12 of 19

Cycle-Free Circuits y

Characterized by absence of cycles among flip-flops, and

a sequential depth, dseq. d i h i b f fli fl h

dseq is the maximum number of flip-flops on any path

between PI and PO.

Both good and faulty circuits are initializable Both good and faulty circuits are initializable. Test sequence length for a fault is bounded by dseq + 1.

Sharif University of Technology Lecture 13: Sequential ATPG Slide 13 of 19

Cycle-Free Example y p

Circuit

F2

Circuit

F3 2 F1 F3 Level = 1 F2 3 F1 F3 2 d 3

s - graph

F1 F3 Level = 1 3 dseq = 3

All faults are testable See Example 8 6

Sharif University of Technology Lecture 13: Sequential ATPG

All faults are testable. See Example 8.6.

Slide 14 of 19

Cyclic Circuit Example y p

Modulo-3 counter CNT Z Modulo-3 counter F1 F2 CNT s - graph F1 F2

Sharif University of Technology Lecture 13: Sequential ATPG Slide 15 of 19

Modulo-3 Counter

Cyclic structure – Sequential depth is undefined. Circuit is not initializable. No tests can be generated for any

stuck-at fault.

Aft

di th i it t 9Nff 81 f ti f

After expanding the circuit to 9Nff = 81, or fewer, time-frames

ATPG program calls any given target fault untestable.

Circuit can only be functionally tested by multiple Circuit can only be functionally tested by multiple

• bservations.

Functional tests, when simulated, give no fault coverage.

Sharif University of Technology Lecture 13: Sequential ATPG Slide 16 of 19

Adding Initializing Hardware Adding Initializing Hardware

Initializable modulo-3 counter CNT Z Initializable modulo-3 counter F1 F2 CNT s-a-0 CLR s-a-1 s-a-1 s-a-1

Untestable fault Potentially detectable fault

s - graph F1 F2

Sharif University of Technology Lecture 13: Sequential ATPG Slide 17 of 19

Benchmark Circuits

Circuit PI PO s1196 14 14 s1238 14 14 s1488 8 19 s1494 8 19 FF Gates Structure Seq depth 18 529 Cycle-free 4 18 508 Cycle-free 4 6 653 Cyclic 6 647 Cyclic

• Seq. depth

Total faults Detected faults Potentially detected faults 4 1242 1239 4 1355 1283

• 1486

1384 2

• 1506

1379 2 Untestable faults Abandoned faults Fault coverage (%) Fault efficiency (%) 3 99.8 100 0 72 94.7 100 0 26 76 93.1 94 8 30 97 91.6 93 4 Fault efficiency (%)

• Max. sequence length

Total test vectors Gentest CPU s (Sparc 2) 100.0 3 313 10 100.0 3 308 15 94.8 24 525 19941 93.4 28 559 19183

Sharif University of Technology Lecture 13: Sequential ATPG Slide 18 of 19

Summary

Combinational ATPG algorithms are extended: Time-frame expansion unrolls time as combinational array Nine-valued logic system Justification via backward time Cycle-free circuits: Cycle free circuits: Require at most dseq time-frames Always initializable Cyclic circuits: May need 9Nff time-frames Circuit must be initializable Partial scan can make circuit cycle-free (Chapter 14) Asynchronous circuits: High complexity Low coverage and unreliable tests Simulation-based methods are more useful (Section 8.3)

Sharif University of Technology Lecture 13: Sequential ATPG

( )

Slide 19 of 19