Red nd nc Remo Red nd nc Remo Redundancy Removal Using ATPG - PowerPoint PPT Presentation

Digital Testing Digital Testing Lecture Lecture 10 10: : Red nd nc Remo Red nd nc Remo Redundancy Removal Using ATPG Redundancy Removal Using ATPG l Usin ATPG l Usin ATPG Instructor: Shaahin Hessabi Instructor: Shaahin Hessabi Department of Computer Engineering Department of Computer Engineering Sharif University of Technology Sharif University of Technology y y gy gy Adapted from lecture notes prepared by the book authors Adapted from lecture notes prepared by the book authors

Irredundant Hardware and Test Patterns Irredundant Hardware and Test Patterns Combinational ATPG can find redundant (unnecessary) hardware Combinational ATPG can find redundant (unnecessary) hardware � Fault Test Fault Test � a sa , b sa 0 A = sa1 1, sa0 = 1 1 a sa , b sa 1 A = sa0 0, sa1 = 0 0 Therefore, these faults are not redundant. Therefore, these faults are not redundant. � � Redundant hardware from testing Redundant hardware from testing g g definition: definition: Combinational hardware that is Combinational hardware that is untestable for SAF is considered as redundant. untestable for SAF is considered as redundant. Two Two- -input AND gate costs input AND gate costs 0 0. .012 012 cents. So, cost cents. So, cost � reduction is not important. reduction is not important. � However, redundant hardware consumes power, H H However, redundant hardware consumes power, d d d d h h d d and is slower (both are critical at present). and is slower (both are critical at present). � Even more critical is the reliability problem Even more critical is the reliability problem (fault masking). (fault masking). Slide 2 of 9 Sharif University of Technology Testability: Lecture 10

Redundant Fault q sa Redundant Fault q sa Redundant Fault Redundant Fault sa1 sa1 1 1 Slide 3 of 9 Sharif University of Technology Testability: Lecture 10

Multiple Fault Masking Multiple Fault Masking Multiple Fault Masking Multiple Fault Masking Multiple Fault Masking Multiple Fault Masking Multiple Fault Masking Multiple Fault Masking � f sa � f sa tested when fault q sa tested when fault q sa sa0 tested when fault sa0 0 tested when fault sa1 sa1 not there 1 not there not there not there Slide 4 of 9 Sharif University of Technology Testability: Lecture 10

Multiple Fault Masking (cont’d) Multiple Fault Masking (cont’d) Multiple Fault Masking (cont’d) Multiple Fault Masking (cont’d) p p p p g ( g ( g ( g ( ) ) ) ) � f sa f masked when fault q sa q sa0 0 masked when fault sa1 1 also present also present p Slide 5 of 9 Sharif University of Technology Testability: Lecture 10

Intentional Redundant Implicant BC BC Intentional Redundant Implicant � Eliminates hazards in circuit output Eliminates hazards in circuit output Slide 6 of 9 Sharif University of Technology Testability: Lecture 10

Fault Cone and D Fault Cone and D- Fault Cone and D Fault Cone and D- -frontier -frontier frontier frontier � Fault Cone Fault Cone -- -- Set of hardware affected by fault Set of hardware affected by fault � D- -frontier frontier – Set of gates closest to POs with fault Set of gates closest to POs with fault effect(s) at input(s). effect(s) at input(s). � Divides circuit into Divides circuit into 2 2 parts: one with fault effects (D and D’), parts: one with fault effects (D and D’), and the other without and the other without and the other without. and the other without. � Set of all gates with D or D’ at inputs and X at the output. Set of all gates with D or D’ at inputs and X at the output. D-fr D-frontier ontier Fault Cone ult Cone Slide 7 of 9 Sharif University of Technology Testability: Lecture 10

Testing as a Global Problem Testing as a Global Problem � Fully Fully- -testable sub testable sub- -assemblies with no redundant assemblies with no redundant logic may be combined into an assembly that logic may be combined into an assembly that logic may be combined into an assembly that logic may be combined into an assembly that has redundant hardware. has redundant hardware. � Slower, Sl Sl Slower, � wastes power, wastes power, � may be unreliable if multiple stuck may be unreliable if multiple stuck- -faults are present faults are present Slide 8 of 9 Sharif University of Technology Testability: Lecture 10

Redundancy Removal Algorithm Redundancy Removal Algorithm Redundancy Removal Algorithm Redundancy Removal Algorithm y y y y g g g g � Impossible for designer to find redundancy. Impossible for designer to find redundancy. � Synopsis synthesis tool synthesizes moderately Synopsis synthesis tool synthesizes moderately-sized y y p p y y y y y y sized designs into irredundant logic. designs into irredundant logic. • Huge designs must be partitioned before synthesis Huge designs must be partitioned before synthesis � potential for potential for redundant hardware redundant hardware � use ATPG for redundancy removal. use ATPG for redundancy removal. y � Removal of one redundant fault may make other Removal of one redundant fault may make other formerly redundant faults testable, so use the formerly redundant faults testable, so use the procedure below: procedure below: d d b l b l Repeat until there are no more redundant faults: Repeat until there are no more redundant faults: { Use ATPG to find all redundant faults; Use ATPG to find all redundant faults; R Remove all redundant faults with non Remove all redundant faults with non- R ll ll d d d d t f t f lt ith lt ith - overlapping fault cone areas; overlapping fault cone areas; } } Slide 9 of 9 Sharif University of Technology Testability: Lecture 10