Red nd nc Remo Red nd nc Remo Redundancy Removal Using ATPG - - PowerPoint PPT Presentation

Digital Testing Digital Testing Lecture Lecture 10 10: :

Red nd nc Remo l Usin ATPG Red nd nc Remo l Usin ATPG Redundancy Removal Using ATPG Redundancy Removal Using ATPG

Instructor: Shaahin Hessabi Instructor: Shaahin Hessabi Department of Computer Engineering Department of Computer Engineering Sharif University of Technology Sharif University of Technology y gy y gy Adapted from lecture notes prepared by the book authors Adapted from lecture notes prepared by the book authors

Irredundant Hardware and Test Patterns Irredundant Hardware and Test Patterns

• Combinational ATPG can find redundant (unnecessary) hardware

Combinational ATPG can find redundant (unnecessary) hardware

• Fault Test

Fault Test a sa sa1 1, , b sa sa0 0 A = = 1 1 a sa sa0 0, , b sa sa1 1 A = = 0

• Therefore, these faults are not redundant.

Therefore, these faults are not redundant.

Redundant hardware from testing

Redundant hardware from testing g g definition: definition: Combinational hardware that is

Combinational hardware that is untestable for SAF is considered as redundant. untestable for SAF is considered as redundant.

• Two

Two-

• input AND gate costs

input AND gate costs 0 0. .012 012 cents. So, cost

• cents. So, cost

reduction is not important. reduction is not important.

H d d h d H d d h d

However, redundant hardware consumes power,

However, redundant hardware consumes power, and is slower (both are critical at present). and is slower (both are critical at present).

Even more critical is the reliability problem

Even more critical is the reliability problem

Slide 2 of 9 Sharif University of Technology Testability: Lecture 10

(fault masking). (fault masking).

Redundant Fault Redundant Fault q sa sa1 1 Redundant Fault Redundant Fault q sa sa1 1

Slide 3 of 9 Sharif University of Technology Testability: Lecture 10

Multiple Fault Masking Multiple Fault Masking Multiple Fault Masking Multiple Fault Masking Multiple Fault Masking Multiple Fault Masking Multiple Fault Masking Multiple Fault Masking

f sa

sa0 tested when fault tested when fault q sa sa1 not there not there

f sa

sa0 0 tested when fault tested when fault q sa sa1 1 not there not there

Slide 4 of 9 Sharif University of Technology Testability: Lecture 10

Multiple Fault Masking (cont’d) Multiple Fault Masking (cont’d) Multiple Fault Masking (cont’d) Multiple Fault Masking (cont’d) p g ( ) p g ( ) p g ( ) p g ( )

f sa

sa0 0 masked when fault masked when fault q sa sa1 1 also present also present f q p

Slide 5 of 9 Sharif University of Technology Testability: Lecture 10

Intentional Redundant Implicant Intentional Redundant Implicant BC BC

Eliminates hazards in circuit output

Eliminates hazards in circuit output

Slide 6 of 9 Sharif University of Technology Testability: Lecture 10

Fault Cone and D Fault Cone and D-

• frontier

frontier Fault Cone and D Fault Cone and D-

• frontier

frontier

Fault Cone

Fault Cone --

• - Set of hardware affected by fault

Set of hardware affected by fault

D-

• frontier

frontier – Set of gates closest to POs with fault Set of gates closest to POs with fault effect(s) at input(s). effect(s) at input(s).

Divides circuit into

Divides circuit into 2 2 parts: one with fault effects (D and D’), parts: one with fault effects (D and D’), and the other without and the other without and the other without. and the other without.

Set of all gates with D or D’ at inputs and X at the output.

Set of all gates with D or D’ at inputs and X at the output. D-fr D-frontier

• ntier

Fault Cone ult Cone

Slide 7 of 9 Sharif University of Technology Testability: Lecture 10

Testing as a Global Problem Testing as a Global Problem

Fully

Fully-

• testable sub

testable sub-

• assemblies with no redundant

assemblies with no redundant logic may be combined into an assembly that logic may be combined into an assembly that logic may be combined into an assembly that logic may be combined into an assembly that has redundant hardware. has redundant hardware.

Sl Sl

Slower,

Slower,

wastes power,

wastes power,

may be unreliable if multiple stuck

may be unreliable if multiple stuck-

• faults are present

faults are present

Slide 8 of 9 Sharif University of Technology Testability: Lecture 10

Redundancy Removal Algorithm Redundancy Removal Algorithm Redundancy Removal Algorithm Redundancy Removal Algorithm y g y g y g y g

Impossible for designer to find redundancy.

Impossible for designer to find redundancy.

Synopsis synthesis tool synthesizes moderately

Synopsis synthesis tool synthesizes moderately-sized sized y p y y y y p y y y designs into irredundant logic. designs into irredundant logic.

• Huge designs must be partitioned before synthesis

Huge designs must be partitioned before synthesis potential for potential for redundant hardware redundant hardware use ATPG for redundancy removal. use ATPG for redundancy removal. y Removal of one redundant fault may make other

Removal of one redundant fault may make other formerly redundant faults testable, so use the formerly redundant faults testable, so use the d b l d b l procedure below: procedure below: Repeat until there are no more redundant faults: Repeat until there are no more redundant faults: { Use ATPG to find all redundant faults; Use ATPG to find all redundant faults; R ll d d t f lt ith R ll d d t f lt ith Remove all redundant faults with non Remove all redundant faults with non-

• verlapping fault cone areas;
• verlapping fault cone areas;

}

Slide 9 of 9 Sharif University of Technology Testability: Lecture 10

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