SoC Design Lecture 9: Platform Based Design Lecture 9: Platform Based Design Shaahin Hessabi Shaahin Hessabi Department of Computer Engineering Sh Sharif University of Technology f U f T h l
Design Methodologies TDD: Timing-Driven Design BBD Bl BBD: Block-Based Design k B d D i PBD: Platform-Based Design 2 SoC: Platform Based Design Sharif University of Technology
Timing-Driven Design � Symptoms requiring a shift from ADD to TDD methodology: � Looping between synthesis and placement without convergence on area and timing p g y p g g � Long turnaround times for each loop to the ASIC vendor � Unanticipated chip-size growth late in the design process � Repeated area, power, and timing re-optimizations � Late creation of adequate manufacturing test vectors � Caused by: � Caused by: � Ineffective or no floor planning at the RTL or gate level � No process for managing and incrementally incorporating late RTL design changes p g g y p g g g into the physical design � Pushing the technology limits beyond what a traditional netlist handoff can support � Ineffective modeling of the chip infrastructure (clock, power, test) during floor � I ff ti d li f th hi i f t t ( l k t t) d i fl planning � Mishandling of datapath logic 3 SoC: Platform Based Design Sharif University of Technology
Timing-Driven Design (cont’d) � Benefits: � Netlist handoff is well understood � Flat-timing analysis / delay calculation is better supported by most of today’s tools � Test generation can be uniform and automatic � Challenges: � High-performance products require iterative loops (place&route timing --> synthesis) � Flat methodology begins to fail as complexity increases (>150 kgates) � Fl t th d l b i t f il l it i (>150 k t ) � Wire-load models are insufficient for high-performance or low-power designs � Main technologies: Main technologies: � Interactive floor-planning tools � Static-timing analysis tools � Using compilers to move design to higher abstractions with timing predictability 4 SoC: Platform Based Design Sharif University of Technology
Block-Based Design � Symptoms when BBD is more appropriate: � Design team is becoming more application-specific, and subsystems, such as embedded g g pp p , y , processing, digital data compression, and error correction, are required � Multiple design teams are formed to work on specific parts of the design � ASIC designers are having difficulty developing realistic testbenches � ASIC d i h i diffi lt d l i li ti t tb h � Interface timing errors between subsystems are increasing dramatically � Design team is looking for VCs outside their group to accelerate product development g g g p p p � Designs employ a bus architecture � processor-determined or custom � Needs a block-level floor planner that quickly estimates RTL block sizes 5 SoC: Platform Based Design Sharif University of Technology
Block-Based Design (cont’d) � Benefits � Top-down design approach manages complexity of large designs p g pp g p y g g � Import of external processor cores supported � Complex, parallel block design teams supported � Challenges � Process does not create a set of reusable components � Constrained by design and re-verification of soft RTL block � C t i d b d i d ifi ti f ft RTL bl k � Limited availability of cycle-accurate and behavioral models � Main technologies Main technologies � Application-specific, high-level algorithmic analysis tools � Block floor planning � Integrated synthesis and physical design 6 SoC: Platform Based Design Sharif University of Technology
Platform-Based Design � Symptoms when PBD is more appropriate: � A significant number of functional design are repeated within and across groups, yet g g p g p , y little reuse is occurring between projects � New convergence markets cannot be engaged with existing expertise and resources � F � Functional design bugs are causing multiple design iterations and/or re-spins ti l d i b i lti l d i it ti d/ i � The competition is getting to market first and getting derivative products out faster � Project post-mortems have shown that architectural trade-off (HW/SW j p ( , VC selection) , ) have been suboptimal � ICs are spending too much time on the test equipment during production, thus rising overall costs overall costs � Pre-existing VCs must be constantly redesigned � Actions to be taken : Actions to be taken : � block authoring; interface standardization; early co-design/co-verification 7 SoC: Platform Based Design Sharif University of Technology
Platform-Based Design (cont’d) � Benefits � Planned design reuse yields very high productivity (and lower costs later on) � Planned design reuse yields very high productivity (and lower costs later on) � Can substantially shorten design cycles � Enables quick derivative designs once the basic platform works � Designs can be composed of diverse, specialized functions from multiple sources � Large share of pre-verified components helps validation for complex designs � Interface-based design promotes higher abstraction design and implementation � Interface based design promotes higher abstraction design and implementation � Challenges � Planned reuse requires significant up-front design planning q g p g p g � Significant SW portions require extensive HW/SW co-verification � Platform migration to new process technology requires re-characterization of VCs (h d (hard and soft) and platform architecture d f ) d l f hi � Limited creativity due to predefined platform components and assembly 8 SoC: Platform Based Design Sharif University of Technology
Platform-Based Design (cont’d) � Main technologies � High-level, system-level algorithmic and architectural design tools and g , y g g hardware/software co-design technologies � Physical layout tools focused on bus planning and block integration � VC-authoring functional verification tools � VC th i f ti l ifi ti t l 9 SoC: Platform Based Design Sharif University of Technology
Comparing Design Methodologies Design characteristics Timing-Driven Design Block-Based Design Platform-Based Design Design complexity g p y 5000 to 250 K gates g 150 K to 1.5 M gates g 300 K gates and greater g g Design level RTL behavioral / RTL Architecture, VC evaluation Design team small, focused multi-disciplinary multi-group, multi-disciplinary Primary design custom logic blocks in context, interfacing to system and bus custom interfaces Design reuse None soft, firm, and hard IP Planned firm and hard Primary optimization Synthesis, gate-level Floor planning, Silicon compatible focus architecture block architecture system architecture Primary design Primary design gates and memory gates and memory functional clusters, functional clusters, VCs VCs granularity cores Bus architecture none / custom custom standardized / multiple application specific pp p Test architecture none / scan scan / JTAG / BIST / hierarchical, parallel custom scan / JTAG / BIST /custom 10 SoC: Platform Based Design Sharif University of Technology
Comparing Design Methodologies (cont’d) Design characteristics Timing-Driven Design Block-Based Design Platform-Based Design Mixed-signal g none A/D, PLL functions, interfaces Verification level RTL / gate bus functional to cycle mixed (ISS to RTL with accurate RTL/gate HW and SW) Hardware/software Hardware/software none none HW/SW functionality HW/SW functionality HW/SW interfaces only HW/SW interfaces only co-verification and interfaces Partitioning focus synthesis limitations functions Functions/communications Placement flat hierarchical hierarchical Routing flat flat hierarchical Timing analysis Timing analysis flat flat flat with limited flat with limited hierarchical hierarchical hierarchy Delay calculation flat flat hierarchical 11 SoC: Platform Based Design Sharif University of Technology
Platform-Based Design “Only the consumer gets freedom of choice; designers need freedom from choice” (Orfali, et al, 1996, p.522) ( , , , p ) � A platform is a restriction on the space of possible implementation choices, providing a well-defined abstraction of the underlying technology for the application developer � New platforms will be defined at the architecture-micro-architecture boundary � They will be component-based, and will provide a range of choices from structured- custom to fully programmable implementations custom to fully programmable implementations � Key to such approaches is the representation of communication in the platform model p 12 SoC: Platform Based Design Sharif University of Technology
The New System Design Paradigm y g g � Separation Separation of function and architecture, of communication and computation � Function: � A function is an abstract view of the behavior of the system. � It is the input/output characterization of the system w.r.t. its environment. � It has no notion of implementation associated to it. 13 SoC: Platform Based Design Sharif University of Technology
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