SoC Design Lecture 9: Platform Based Design Lecture 9: Platform - - PowerPoint PPT Presentation

SoC Design Lecture 9: Platform Based Design

Shaahin Hessabi

Lecture 9: Platform Based Design

Shaahin Hessabi Department of Computer Engineering Sh f U f T h l Sharif University of Technology

Design Methodologies

TDD: Timing-Driven Design BBD Bl k B d D i BBD: Block-Based Design PBD: Platform-Based Design

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Timing-Driven Design

Symptoms requiring a shift from ADD to TDD methodology:

Looping between synthesis and placement without convergence on area and timing

p g y p g g

Long turnaround times for each loop to the ASIC vendor Unanticipated chip-size growth late in the design process Repeated area, power, and timing re-optimizations Late creation of adequate manufacturing test vectors

Caused by: Caused by:

Ineffective or no floor planning at the RTL or gate level No process for managing and incrementally incorporating late RTL design changes

p g g y p g g g into the physical design

Pushing the technology limits beyond what a traditional netlist handoff can support I

ff ti d li f th hi i f t t ( l k t t) d i fl

Ineffective modeling of the chip infrastructure (clock, power, test) during floor

planning

Mishandling of datapath logic

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Timing-Driven Design (cont’d)

Benefits:

Netlist handoff is well understood Flat-timing analysis / delay calculation is better supported by most of today’s tools Test generation can be uniform and automatic

Challenges:

High-performance products require iterative loops (place&route timing --> synthesis) Fl t

th d l b i t f il l it i (>150 k t )

Flat methodology begins to fail as complexity increases (>150 kgates) Wire-load models are insufficient for high-performance or low-power designs

Main technologies:

Main technologies:

Interactive floor-planning tools Static-timing analysis tools Using compilers to move design to higher abstractions with timing predictability

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Block-Based Design

Symptoms when BBD is more appropriate:

Design team is becoming more application-specific, and subsystems, such as embedded

g g pp p , y , processing, digital data compression, and error correction, are required

Multiple design teams are formed to work on specific parts of the design ASIC d i

h i diffi lt d l i li ti t tb h

ASIC designers are having difficulty developing realistic testbenches Interface timing errors between subsystems are increasing dramatically Design team is looking for VCs outside their group to accelerate product development

g g g p p p Designs employ a bus architecture

processor-determined or custom

Needs a block-level floor planner that quickly estimates RTL block sizes

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Block-Based Design (cont’d)

Benefits

Top-down design approach manages complexity of large designs

p g pp g p y g g

Import of external processor cores supported Complex, parallel block design teams supported

Challenges

Process does not create a set of reusable components C

t i d b d i d ifi ti f ft RTL bl k

Constrained by design and re-verification of soft RTL block Limited availability of cycle-accurate and behavioral models

Main technologies

Main technologies

Application-specific, high-level algorithmic analysis tools Block floor planning Integrated synthesis and physical design

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Platform-Based Design

Symptoms when PBD is more appropriate:

A significant number of functional design are repeated within and across groups, yet

g g p g p , y little reuse is occurring between projects

New convergence markets cannot be engaged with existing expertise and resources F

ti l d i b i lti l d i it ti d/ i

Functional design bugs are causing multiple design iterations and/or re-spins The competition is getting to market first and getting derivative products out faster Project post-mortems have shown that architectural trade-off (HW/SW

, VC selection) j p ( , ) have been suboptimal

ICs are spending too much time on the test equipment during production, thus rising

• verall costs
• verall costs

Pre-existing VCs must be constantly redesigned

Actions to be taken:

Actions to be taken:

block authoring; interface standardization; early co-design/co-verification

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Platform-Based Design (cont’d)

Benefits

Planned design reuse yields very high productivity (and lower costs later on) Planned design reuse yields very high productivity (and lower costs later on)

Can substantially shorten design cycles Enables quick derivative designs once the basic platform works

Designs can be composed of diverse, specialized functions from multiple sources Large share of pre-verified components helps validation for complex designs Interface-based design promotes higher abstraction design and implementation Interface based design promotes higher abstraction design and implementation

Challenges

Planned reuse requires significant up-front design planning

q g p g p g

Significant SW portions require extensive HW/SW co-verification Platform migration to new process technology requires re-characterization of VCs

(h d d f ) d l f hi (hard and soft) and platform architecture

Limited creativity due to predefined platform components and assembly

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Platform-Based Design (cont’d)

Main technologies

High-level, system-level algorithmic and architectural design tools and

g , y g g hardware/software co-design technologies

Physical layout tools focused on bus planning and block integration VC

th i f ti l ifi ti t l

VC-authoring functional verification tools

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Comparing Design Methodologies

Design characteristics Timing-Driven Design Block-Based Design Platform-Based Design

Design complexity 5000 to 250 K gates 150 K to 1.5 M gates 300 K gates and greater g p y g g g g Design level RTL behavioral / RTL Architecture, VC evaluation Design team small, focused multi-disciplinary multi-group, multi-disciplinary Primary design custom logic blocks in context, custom interfaces interfacing to system and bus Design reuse None soft, firm, and hard IP Planned firm and hard Primary optimization focus Synthesis, gate-level architecture Floor planning, block architecture Silicon compatible system architecture Primary design gates and memory functional clusters, VCs Primary design granularity gates and memory functional clusters, cores VCs Bus architecture none / custom custom standardized / multiple application specific pp p Test architecture none / scan scan / JTAG / BIST / custom hierarchical, parallel scan / JTAG / BIST /custom

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Comparing Design Methodologies (cont’d)

Design characteristics Timing-Driven Design Block-Based Design Platform-Based Design

Mixed-signal none A/D, PLL functions, interfaces g Verification level RTL / gate bus functional to cycle accurate RTL/gate mixed (ISS to RTL with HW and SW) Hardware/software none HW/SW functionality HW/SW interfaces only Hardware/software co-verification none HW/SW functionality and interfaces HW/SW interfaces only Partitioning focus synthesis limitations functions Functions/communications Placement flat hierarchical hierarchical Routing flat flat hierarchical Timing analysis flat flat with limited hierarchical Timing analysis flat flat with limited hierarchy hierarchical Delay calculation flat flat hierarchical

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Platform-Based Design

“Only the consumer gets freedom of choice; designers need freedom from choice” (Orfali, et al, 1996, p.522) ( , , , p )

A platform is a restriction on the space of possible implementation

choices, providing a well-defined abstraction of the underlying technology for the application developer

New platforms will be defined at the architecture-micro-architecture

boundary

They will be component-based, and will provide a range of choices from structured-

custom to fully programmable implementations custom to fully programmable implementations Key to such approaches is the representation of communication in the

platform model p

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The New System Design Paradigm y g g

Separation

Separation

• f function and architecture,
• f communication and computation

Function:

A function is an abstract view of the behavior of the system. It is the input/output characterization of the system w.r.t. its environment. It has no notion of implementation associated to it.

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Terms

Architecture

An architecture is a set of components, either abstract or with a physical dimension,

that is used to implement a function. Architecture platform: A fixed set of components with some degrees of

i bilit i f di i f f it t variability in performance or dimensions of one or more of its components

Communication

Communication provides for the transmission of data and control information between Communication provides for the transmission of data and control information between

functions and with the outside world. Communication layers:

y

Transaction: Point-to-point transfers between VCs.

Covers the range of possible options and responses (VC interface).

B T

f P l d f d b b

Bus Transfer: Protocols used to transfer data between two components across a bus. Physical : Deals with physical wiring of the buses, drive, and timing specific to process

technology.

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gy

Design Flow and Architecture Template g p

Template: an architecture

with parameters and rules with parameters and rules that define what is (not) allowed.

Platform-based design

flow:

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Syst stem-on-Chi em-on-Chip Platf Platform rm y p

Layered concept allows to

Change the physical architecture of the SoC

without affecting the application

Add new services on top of existing architecture

p g Changes in one layer affect only the layer

itself and its interfaces

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PC Platform

The most successful application of platform concept for reuse.

x86 ISA (makes it possible to re-use OS and software applications at binary level).

( p pp y )

fully specified set of busses (ISA, USB, PCI). legacy support for the ISA interrupt controller. fully specified set of I/O devices.

Too rigid (and expensive) for embedded system applications

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Platform-Based Integration

A fully defined architecture with

Bus structure Clocking/power distribution OS

A collection of IP blocks Architecture reuse

The definition of a hardware platform is the result of a trade-off process involving reusability, production cost and performance optimization.

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Hardware Platform

Hardware Platform: not only a fully specified SoC, but also a family of

architectures that:

share some common features, satisfy a set of architectural constraints imposed to allow the re-use of hardware and

f software components.

The stronger the constraints the more component re-use

but stronger constraints imply fewer architectures to choose from!

Hardware platforms is not enough:

Hardware platform has to be abstracted. Interface to the application software is API. Software layer performs abstraction:

Programmable cores and memory subsystem with RTOS Programmable cores and memory subsystem with RTOS. I/O subsystem via Device Drivers. Sharif University of Technology SoC: Platform Based Design 19

Platform Based Design

Very little difference with top down design. Partitioning is known, so no partitioning step.

g , p g p

Part of the executable model is handed over to SW developer for optimization. HW and SW still modeled in one unified model. SW and HW people still work in parallel, refining and optimizing their designs. HW platform is built separately.

This can be used as a virtual platform for the SW developers to develop their SW on.

SW people can work in their preferred environment. Less concurrency in HW and SW development. Concurrency still possible: HW platform is delivered at a higher level of

abstraction on hich SW people do de elopment hile HW people are further abstraction, on which SW people do development, while HW people are further refining to lower levels of abstraction.

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How Platform-Based Design Works?

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Ingredients of a Platform g

Cores

P

IP Validation

HW/SW C V ifi ti Processor IP Bus/Interconnection Peripheral IP HW/SW Co-Verification Compliance test suites

Prototyping p

Application specific IP

Software

Prototyping

HW emulation FPGA based prototyping Drivers Firmware (R l ti

) OS

Platform prototypes (i.e. dedicated

prototyping devices)

SW prototyping (Real-time) OS Application software/libraries SW prototyping

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How to Build a Platform

Architecture constraints for an integration platform: 1

Pick your application domain

1.

Pick your application domain

2.

Pick your on-chip communications architecture and structure (levels and structure of buses/private communications) p )

3.

Pick your Star IP (e.g. processors)

• Processors: drag along detailed communications choices, e.g. processor busses

g g g p 4.

Dedicated memory access, etc. -ARM-AMBA, etc. Also limit e.g. RTOS

5.

Pick application specific HW and SW IP pp p

6.

Other IP blocks not wrapped to the on-chip communications may work with IP wrappers. VSI Alliance VCI is a good choice to start with for an adaptation layer

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Types of Platform

According to the strength of constraints on hardware

Fixed Platforms

stronger

Fixed Platforms

Software-oriented: TI's OMAPTM, Philips Nexperia.. Application-specific: Ericsson’s BCP

,

Configurable platforms

Bus structure, multiple processors, programmable logic devices: Altera's

ExcaliburTM, Triscend’s CSoC, Philips RSP , Cypress MicroSystems’ PSoCTM

Programmable platforms

Improv’s PSATM Jazz

weaker

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Triscend E5 CSoC

Triscend: the pioneer in commercially providing Programmable SoC

• devices. Introduced in 1999, E5 chips are equipped with 8032-compatible

, p q pp p processor; hence, suitable for control-dominated applications. Features:

Performance accelerated 8051 core (10MIPS at 40MHz) S

d l i f i l l

Standalone operation from a single external memory

(code + configuration)

Up to 64Kbytes of on-chip, dedicated system RAM Up to 3200 Configurable System Logic (CSL) cells Up to 3200 Configurable System Logic (CSL) cells (up to 40,000 "ASIC" gates) Power-down and power-management modes Compliant to the "CSI Socket" interface allowing soft Compliant to the CSI Socket interface, allowing soft

peripherals to be used on other CSoC Families

Two dedicated DMA Channels On-chip breakpoint unit provides sophisticated

p p p p debugging capability

Offers real-time debugging for hw/sw co-verification Sharif University of Technology SoC: Platform Based Design 25

Triscend A7 CSoC

Industry’s first 32-bit Programmable SoC, is based on ARM7TDMI RISC

processor Features

• processor. Features:

High-performance, 32-bit ARM7TDMI™

Processor Core Processor Core

Memory Interface Unit Flexible, glue-less interface to external

memories (ROM, EEPROM, FLASH, SRAM d SDRAM) SRAM, and SDRAM)

8-bit, 16-bit and 32-bit support Up to 2 external SDRAM banks Automatic support for self-refresh, auto- Automatic support for self refresh, auto

refresh and initialization of SDRAM

4-channel DMA controller In-system debug/breakpoint unit P

d d d

Power-down and power-management modes CSL cells can be configured as memory,

including true dual-port operation

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Atmel FPSLIC

FPSLIC: Field-Programmable

System Level Integrated Circuit System-Level Integrated Circuit

Introduced in 1999, as Triscend E5,

is equipped with Atmel’s own 20 is equipped with Atmel s own 20 MIPS, 8-bit RISC processor.

FPSLIC Secure (AT94S) chips

FPSLIC Secure (AT94S) chips integrate configuration memory in the programmable SoC device to provide more security.

Software tool provides hw-sw co-

simulation capability.

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Cypress MicroSystems PSoC

Eight 8-bit digital PSoC blocks

4 Digital Basic Type A blocks: Timer/Counter/Shifter/CRC/PRS/Deadband functions 4 Digital Communications blocks:

Timer/Counter/Shifter/CRC/PRS/Deadband functions Full-duplex UARTs and SPI master or slave functions

p

Twelve analog PSoC blocks 3 types: ContinuousTime (CT)

blocks and type 1 and type 2 Switch blocks, and type 1 and type 2 Switch Capacitor (SC) blocks that support 14-bit Multi-Slope and 12 bit Delta- Sigma ADC, successive g , approximation ADCs up to 9 bits, DACs up to 9 bits, programmable gain stages, sample and hold g g , p circuits, programmable filters, differential comparators, and temperature sensor

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Altera Excalibur Nios Family

Soft-core processor embedded on an

Apex20K FPGA, taking 2% of FPGA p , g logic capacity.

Compiler : GNUPro C compiler, and

Quartus is used to design and implement the hardware portion.

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Alt Altera ra - Excalibur aliburTM

TM ARM-Based F

ARM-Based Famil mily

Industry-standard ARM922T 32-bit RISC

processor core operating at up to 200 p p g p MHz

Memory management unit (MMU) included

Builds upon features of the APEX 20KE

family, with up to 1,000,000 gates

H

d h hi i h 8

Harvard cache architecture with separate 8-

Kbyte instruction and 8-Kbyte data caches

Internal single-port and dual port SRAMs

g p p

External SDRAM External flash memory

l h h l l d T

Several on-chip peripherals including ETM9

embedded trace module, interrupt controller, UART, timer, and watchdog timer

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Xilinx VirtexII PowerPC Based

Refer to lecture 4

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SoC Platform Example: Bluetooth SoC Platform Example: Bluetooth

Bluetooth: used for low-power wireless personal area networks (WPANs). Overall architecture consists of an RF front-end, a baseband controller,

and software to implement the Bluetooth protocol stack.

Bluetooth architecture Bluetooth protocol stack

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p

Bluetooth Protocol

Enables users to make instant connections between a wide range of

communication devices

Complete wireless specification and link with normal modules up to 10 m

• r, up to 100 meters, with a power amplifier

Supports up to seven simultaneous links Data rate of 1 Mega symbols per second

g y p

Operates in the Industrial, Scientific, and Medical (ISM) frequency band of

2.4 GHz, ensuring worldwide communication compatibility

Frequency-hopping radio link for fast and secure voice/data transmission Supports point-to-point, point-to-multipoint (including broadcast)

connectivity

Low power consumption

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Baseband Processing Unit of Bluetooth

WPAN is a suitable application for platform-based design: 1

Enormous hardware software design and verification flows technology

1.

Enormous hardware, software, design and verification flows, technology, and testing issues are prohibitive in the market windows associated with this type of product.

2.

Bluetooth standard is upgraded or customer requirements shift, so design may become obsolete.

3.

Other PAN standards under development with similar characteristics.

Platform concept will be illustrated with design process of the baseband

processing unit of Bluetooth.

Software portion of the protocol stack runs on ARM7TDMI processor.

Responsible for Bluetooth functions associated with establishing connections between

devices, and interpreting the packets to determine the services requested by other devices.

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Bluetooth Baseband Platform

S l h l “S Chi R d I i ” P di f h IEEE J 2006

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Saleh et al., “System-on-Chip: Reuse and Integration,” Proceedings of the IEEE, June 2006

Components of Bluetooth Baseband p

The ARM7 processor requires high-speed connections to certain blocks:

shared memory controller (SMC), direct memory access (DMA) controller, test

y ( ), y ( ) , interface controller (TIC), and power and clock control units. Connections can be implemented using the synchronous advanced high-

speed bus (AHB) of the AMBA bus standard.

Bus requires development of a bus arbiter and decoder functions. Arbiter: Ensures that only one bus master initiates data transfers at a time Arbiter: Ensures that only one bus master initiates data transfers at a time Decoder: Performs decoding of the transfer addresses and selects slaves appropriately

The other components in the system operate at different speeds and are

p y p p connected using the asynchronous advanced peripheral bus (APB).

Components include: watchdog and other timers, general-purpose input/output

(GPIO) devices, programmable interrupt controller (PIC), UART, and USB interface standards.

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Components of Bluetooth Baseband

Baseband Controller (BBC) performs the DSP functions on the incoming

and outgoing bit streams and radio control functions, and is interfaced to g g , the APB.

Bus bridge is used to interface the AHB to the APB. Programmability in the platform:

1.

ARM processor is programmable,

2.

Local embedded FPGA to speed up critical sections of the code in protocol stack

3.

Other interface blocks can be replaced by a similar embedded FPGA

so long as the resulting fabric does not consume a large area or exceed the power so long as the resulting fabric does not consume a large area or exceed the power

specifications of Bluetooth

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