Using the new TLM-2.0 Standard for the Creation of Virtual Platforms for ESL Design Dr. Tim Kogel Office of the CTO CoWare, Inc. 1 Overview Overview MP-SoC Trends and Challenges ESL Design Solutions – Design Tasks and Requirements – Enabling technologies 2 2
Design Trends Design Trends Device Multi-media convergence digital TV Multi-media access Wireless connectivity Automotive anytime, anywhere Smart Infotainment phone High definition Multi-functional picture printer Imaging anywhere Gaming Multi-media PC HW Centric SW and HW Centric Local memory subsystem Complex memory hierarchy Local, shared bus Intelligent interconnect (NoC) Single processor Multiple processor Single SW stack Multiple, dependent SW stacks 3 3 Transition from ASIC to MPSoC Transition from ASIC to MPSoC Complex ASIC SW Driven Design ASIC Cost • High Definition • Exploding SW content? • Convergence • Higher clock frequency? • Wireless Everywhere • Increased memory? MP-SoC Power Custom CPU DSP DSP Multi Core SoC Energy Efficiency I/O I/O I/O FPGA eMEM FPGA MEM Periph • Portable devices? 4 4
Design Challenges Design Challenges 24% of projects canceled due to schedule slip 54% of SW designs completed behind schedule 33% of devices miss functionality/performance 80% of effort to correct errors discovered late System Architecture Design Project Management Top issues Board-level engineering Firmware development System integration Architecture Application development Software SoC design/verification OS development Integration Algorithm design 5 Source: 5 MP-SoC Design Flow Challenges MP-SoC Design Flow Challenges Feedback to supplier ecosystem Delivery to partner ecosystem Customer Customer Development requirements Marketing Marketing RTL Logic HW re-use sign-off sign-off sign-off P IP RTL SoC RTL Logic Layout Manufacturing R Hardware design O Maintenance D Arch. Paper Bring-up Sys. test design spec. U Support Software dev. C T SW stacks SW re-use and UML OS, Objects Multi- Documentation Components SW API core Seq. language 6 Compiler, IDE Asm 6 Assembler, Linker, Loader
Solution: ESL Design Solution: ESL Design Feedback to supplier ecosystem Early Delivery to partner ecosystem Design Customer Customer Engagements: Requirements –Validation – Development - Support Customer Development requirements Wins � � � � � � Marketing Marketing Marketing P Hardware design R Manufacturing Increased O … with virtual platforms Arch. Paper Bring- Sys. Productivity Maintenance test D Concurrent up Continuous Bring-up Sys. test design spec. design integration Predictability U Support Software dev. C Quality T Documentation 7 7 Overview Overview MP-SoC Trends and Challenges ESL Design Solutions – Design Tasks and Requirements – Enabling technologies 8 8
Need virtual platforms for … Need virtual platforms for … Application Sub- Performance Systems Design Validation Serial WWW SRAM/FLASH/ROM Software Development Tools RAM DSP I2C UART Ethernet Controller DSP (Program & firmware & Core(s) Data) applications Bus Operating Interconnect Interconnect GPIO Timer Processor Controller Systems & Core(s) Applications Smart Bridge Card DMA Interrupt Real Time Video Controller Controller Clock Programmable Subsystem Multi-layer Firmware Accelerator fabric Display Watchdog DDR DVB-T Controller Timer Controller Display Analog External DDR Front End Software See also: OSCI TLM-2 Requirements, Development Section 2 "Definition of TLM Use-Cases“ Platform Architecture http://www.systemc.org/downloads/drafts_review/ Design 9 9 Software Application Development Software Application Development Software Debugger Virtual Platform Analyzer Keypad/Display Device Requirements – Sufficient simulation speed (10-50% real-time) – Functional completeness and register accuracy – Timing accuracy: software synchronization – Controllability and observability Console – Integration with Software IDEs – External connectivity SystemC Virtual Platform 10 10
Software Performance Analysis Software Performance Analysis Software Performance Analysis Hardware Performance Analysis Requirements – Sufficient simulation speed (1-10% real-time) – Functional completeness and register accuracy – Timing accuracy: 80% (interval: ~100k cycles) – Hardware and software performance analysis views – External connectivity SystemC Virtual Platform 11 11 Architecture Analysis Architecture Analysis Workload modeling options: – Trace-driven File Reader Bus Master – Task-graph driven Virtual Processing Unit Hardware Performance Analysis Requirements – Sufficient simulation speed (100-1000 x RTL) – Cycle-accurate models of critical components • Interconnect, memory subsystem – Same level of configurability as real IP – Timing accuracy: 95% (interval: 1-10 cycles) – Hardware performance analysis views SystemC Virtual Platform 12 12
Example: Performance Validation Example: Performance Validation Software Performance Analysis Hardware Performance Analysis Requirements – Sufficient simulation speed (50-500 x RTL) – Cycle-accurate models of critical components • Processor, interconnect, memory subsystem – Functional completeness and register accuracy – Timing accuracy: 95% (interval: 1-10 cycles) – Hardware and software performance analysis views SystemC Virtual Platform 13 13 Overview Overview MP-SoC Trends and Challenges ESL Design Solutions – Design Tasks and Requirements – Enabling technologies 14 14
Outline Outline TLM-2.0 Standard Overview – Concepts and APIs – The Loosely Timed Modeling Style – The Approximately Timed Modeling Style Effective Creation of TLM-2.0 Peripheral Models Creating TLM-2.0 based Virtual Platforms 15 15 OSCI TLM WG OSCI TLM WG Source: OSCI SystemC Community Update, DATE 2007 120 individuals from 27 organizations ~20 individuals from ~17 organizations participate regularly in weekly 2-hour teleconference 16 16 16
TLM-2.0 Overview TLM-2.0 Overview TLM Use-Cases SW Application SW Performance Architecture Performance Development Analysis Analysis Validation TLM-2.0 Modeling Styles Loosely-timed Multi-phase, non-blocking API Single-phase, blocking API Approximately-timed Blocking Generic Non-blocking DMI Quantum Sockets Extensions Phases interface payload interface TLM-2.0 Mechanisms 17 17 Generic Payload Generic Payload Typical set of memory mapped bus attributes command : enum, READ, WRITE, IGNORE address : uint64, byte address data : unsigned char*, pointer to storage length : unsigned int, number of bytes in the data array byte_enable : unsigned char*, species sub-word accesses byte_enable_length : unsigned int, number of elements in byte_enable streaming_width : unsigned int, defines a streaming burst response_status : enum, INCOMPLETE, OK, ERROR-code Extension mechanism – Array of pointers to user defined payload extensions – Defines rules for ignorable and mandatory extensions Memory Management – Reference counting mechanism – Mandatory for AT, optional for LT Helper functions for endianness conversion 18 18
TLM-2.0 Overview TLM-2.0 Overview TLM Use-Cases SW Application SW Performance Architecture Performance Development Analysis Analysis Validation TLM-2.0 Modeling Styles Loosely-timed Multi-phase, non-blocking API Single-phase, blocking API Approximately-timed Blocking Generic Non-blocking DMI Quantum Sockets Extensions Phases interface payload interface TLM-2.0 Mechanisms 19 19 Blocking Transport Blocking Transport Initiator Target Initiator Target port port port port b_transport b_transport Interconnect Interconnect Initiator Target Initiator Target component component tlm_blocking_transport_if { void b_transport ( TRANS& trans , sc_core::sc_time& t ); }; Simple API, support for timing annotation, addressing all SW related ESL Design tasks 20 Sources: OSCI and CoWare (adapted from the TLM-2 Draft 2 manual) 20
Blocking Transport Blocking Transport Initiator Target Simulation time = 100ns b_transport(trans,0) Call wait(10ns) Simulation time = 110ns Return Initiator is blocked until return from b_transport 21 21 Loosely-timed with Timing Annotation Loosely-timed with Timing Annotation Target Initiator sc_time parameter Simulation time = 1000ns as specified by initiator Local time b_transport(trans,0ns) Call +0ns Return b_transport(trans,10ns) updated sc_time parameter as specified by target +10ns Transaction completed immediately with timing annotation 22 22
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