13 IO Systems IO - PowerPoint PPT Presentation

. . May 28, 2014 May 28, 2014 . . . . . . . . . . . 1 / 41 操作系统原理与设计 第 13 章 IO Systems （ IO 管理） 陈香兰 中国科学技术大学计算机学院 陈香兰 ( 中国科学技术大学计算机学院 ) 操作系统原理与设计

. .. 3 Kernel I/O Subsystem I/O Scheduling Caching, Spooling & device reservation Error Handling I/O Protection Kernel Data Structures . 4 . Transforming I/O Requests to Hardware Operations . .. 5 Performance . .. 6 May 28, 2014 .. . Clocks and Timers I/O Hardware . . . . . . . .. 1 2 / 41 2 Network Devices Block and Character Devices I/O hardware summary . Application I/O Interface .. 提纲 Polling ( 轮询方式 ) Interrupts ( 中断方式 ) Direct Memory Access (DMA 方式 ) Blocking ( 阻塞 ) and Nonblocking ( 非阻塞 ) I/O Buffering ( 缓冲机制 ) 小结和作业 陈香兰 ( 中国科学技术大学计算机学院 ) 操作系统原理与设计

. . . . . . Chapter Objectives Explore the structure of an OS’s I/O subsystem. Discuss the principles of I/O hardware and its complexity. Provide details of the performance aspects of I/O hardware and software. May 28, 2014 3 / 41 陈香兰 ( 中国科学技术大学计算机学院 ) 操作系统原理与设计

. . May 28, 2014 . . . . . . . of OS designers. The control of devices connected to the computer is a major concern vary widely I/O devices Overview . . . . 4 / 41 How OS manages and controls various peripherals ？ 陈香兰 ( 中国科学技术大学计算机学院 ) 操作系统原理与设计

. Transforming I/O Requests to Hardware Operations .. 3 Kernel I/O Subsystem . .. 4 . . .. 5 Performance . .. 6 May 28, 2014 . Application I/O Interface 2 . . . . . Outline . .. . .. 1 I/O Hardware I/O hardware summary . 5 / 41 Polling ( 轮询方式 ) Interrupts ( 中断方式 ) Direct Memory Access (DMA 方式 ) 小结和作业 陈香兰 ( 中国科学技术大学计算机学院 ) 操作系统原理与设计

. . . . . . I/O Hardware . . Incredible variety of I/O devices May 28, 2014 6 / 41 陈香兰 ( 中国科学技术大学计算机学院 ) 操作系统原理与设计

. . May 28, 2014 I/O instructions control devices bit patterns in the registers. The process communicates with the controller by reading and writing Controller has one or more registers for data and control signals. How can the processor command controller? Expansion bus SCSI (Small computer systems interface) PCI (Peripheral Component Interconnect ) . . I/O Hardware . . . . 6 / 41 Common concepts : CPU → PORT → BUS → Controller Port ( 端口 ) Bus ( 总线 ) (daisy chain or shared direct access) Controller ( 控制器 ) (host adapter) 陈香兰 ( 中国科学技术大学计算机学院 ) 操作系统原理与设计

. Direct I/O instructions May 28, 2014 routines Memory-mapped I/O 2 . . . Instructions: In, out data-in and data-out. Each port typically contains of four registers, i.e., status, control, . Access the port address 1 . . . Two communication approaches . . I/O Hardware . . . . 6 / 41 Example: 0xa0000 ˜ 0xfffff are reserved to ISA graphics cards and BIOS 陈香兰 ( 中国科学技术大学计算机学院 ) 操作系统原理与设计

. parallel port game controller 2F8-2FF serial port (secondary) 320-32F hard-disk controller 378-37F 3D0-3DF . graphics controller 3F0-3F7 diskette-drive controller 3F8-3FF serial port (primary) May 28, 2014 200-20F timer 040-043 interrupt controller . . . . I/O Hardware . . I/O address range Device I/O Port Locations on PCs (partial) I/O address range (hexadecimal) device 000-00F DMA controller 020-021 6 / 41 陈香兰 ( 中国科学技术大学计算机学院 ) 操作系统原理与设计

. . May 28, 2014 . . . . . . . . . . . . I/O Control Methods . . . . 7 / 41 1 Polling ( 轮询方式 ) 2 Interrupts ( 中断方式 ) 3 DMA (DMA 方式 ) 4 ( 在汤书上：还有通道的概念 ) 陈香兰 ( 中国科学技术大学计算机学院 ) 操作系统原理与设计

. . May 28, 2014 To indicate whether an I/O is ok. Error 3 . . . 0: ready for the next command; 1: busy In status register busy 2 . . . 1: a command is available for the controller In command register . . . . . command-ready . State of device . . . 1 8 / 41 Polling ( 轮询方式 ) Need handshaking ( 握手 ) 陈香兰 ( 中国科学技术大学计算机学院 ) 操作系统原理与设计

. . 3 Host sets command-ready bit . . . 4 When controller notices command-ready, sets busy bit . . . 5 Controller gets write command and data, and works . . . 6 Controller clears command-ready bit, error bit and busy bit May 28, 2014 . . . . . . . . . . register Basic handshaking notion for writing output . . 1 Host repeatedly reads the busy bit until it is 0 . . . 2 Host sets write bit in command register and writes a byte into data-out 8 / 41 Polling ( 轮询方式 ) Step1: Busy-wait cycle to wait for I/O from device ≡ polling 陈香兰 ( 中国科学技术大学计算机学院 ) 操作系统原理与设计

. Devices May 28, 2014 CPU OS master 8259 slave 8259 . 9 / 41 Basic interrupt scheme Interrupt handler receives interrupts . . . . . CPU Interrupt-request line triggered by I/O device . Interrupts ( 中断方式 ) Raise → Catch → Dispatch → Clear ✲ ✲ ✲ ✲ ✲ ✲ ✲ ✲ ✲ ✲ ✲ ✲ ✲ ✲ ✲ ✲ 陈香兰 ( 中国科学技术大学计算机学院 ) 操作系统原理与设计

. 3 5 CPU executing checks for interrupts between instructions device driver initiates I/O 2 initiates I/O input ready, output . complete, or error generates interrupt signal 4 1 CPU I/O controller May 28, 2014 interrupt handler transfers control to CPU receiveing interrupt, Interrupt-Driven I/O Cycle . . . . . 6 . CPU resumes processing of interrupted task 7 interrupt handler processes data, returns from interrupt 9 / 41 Interrupts ( 中断方式 ) 陈香兰 ( 中国科学技术大学计算机学院 ) 操作系统原理与设计

. . May 28, 2014 Interrupt mechanism also used for exceptions Interrupt priority Distinguish between high- and low-priority interrupts Interrupt chaining : to allow more device & more interrupt handlers Interrupt vector to dispatch interrupt to correct handler Efficient dispatching without polling the devices Nonmaskable Maskable to ignore or delay some interrupts Defer interrupt handling More sophisticated interrupt-handling features . . . . . . 9 / 41 Interrupts ( 中断方式 ) 陈香兰 ( 中国科学技术大学计算机学院 ) 操作系统原理与设计

. device not available 15 (Intel reserved, do not use) 5 bound range exception 16 floating-point error 6 invalid opcode 17 alignment check 7 18 . machine check 8 double fault 19-31 (Intel reserved, do not use) 9 coprocessor segment overrun (reserved) 32-255 maskable interrupts 10 invalid task state segment May 28, 2014 INTO-detected overflow 4 page fault 14 . . . . . . Example: Intel Pentium Processor Event-Vector Table vector number description vector number description 0 divide error 11 breakpoint 3 general protection 13 null interrupt 2 stack fault 12 debug exception 1 segment no present 9 / 41 Interrupts ( 中断方式 ) 陈香兰 ( 中国科学技术大学计算机学院 ) 操作系统原理与设计

. . May 28, 2014 controller, and then goes on with other work. CPU writes the address of the DMA command block to DMA a count of the number of bytes to be transfered a pointer to the destination of the transfer a pointer to the source of a transfer the host prepares a DMA command block in memory DMA controller Requires memory Used to avoid programmed I/O for large data movement , and . . . . . . 10 / 41 Direct Memory Access (DMA 方式 ) Direct Memory Access (DMA 方式 ): bypasses CPU to transfer data directly between I/O device and 陈香兰 ( 中国科学技术大学计算机学院 ) 操作系统原理与设计

. . May 28, 2014 DMA controller interrupts the CPU. 4 . . . DMA-request signal. Goto 1 Device controller transfers the word to memory, and removes the 3 . . . memory-address wires, and raises DMA-acknowledge DMA controller seizes memory bus , places the desired address on 2 . . . . . . . . Handshaking between DMA controller & device controller . . . 1 Device controller raises DMA-request when one word is available . 10 / 41 Direct Memory Access (DMA 方式 ) 陈香兰 ( 中国科学技术大学计算机学院 ) 操作系统原理与设计

. . . . . . . . Six Step Process to Perform DMA Transfer Cycle stealing: when DMA seizes the memory bus, CPU is momentarily prevented from accessing main memory May 28, 2014 10 / 41 Direct Memory Access (DMA 方式 ) 陈香兰 ( 中国科学技术大学计算机学院 ) 操作系统原理与设计

. . May 28, 2014 the offloading of this work to a DMA controller for large transfer The execution of this handshaing in a pooling loop via interrupts The handshaking relationship between the host and a device controller An I/O port and its registers A controller A bus I/O hardware summary . . . . 11 / 41 陈香兰 ( 中国科学技术大学计算机学院 ) 操作系统原理与设计