Digital Testing L Lecture 1 t 1 Instructor: Shaahin Hessabi Department of Computer Engineering p p g g Sharif University of Technology Adapted from lecture notes prepared by the book authors Slide 1 of 18
Introduction � Course outline � VLSI realization process � VLSI realization process � Verification and test � Ideal and real tests � Ideal and real tests � Costs of testing � Roles of testing � Roles of testing Sharif University of Technology Digital Testing: Chapter 1 Slide 2 of 18
Class Goals � To educate the general digital systems designer on the fundamentals of test technology in a manner that will assist him/her in designing testable systems � provide information on the goals and techniques for testing � provide information on the goals and techniques for testing systems � provide information on techniques to increase the testability of designs � provide information on how to incorporate these techniques into a general digital design methodology into a general digital design methodology Sharif University of Technology Digital Testing: Chapter 1 Slide 3 of 18
Course Outline Part I: Introduction � Basic concepts and definitions (Chapter 1) � Test process and ATE (Chapter 2) � Test economics and product quality (Chapter 3) p q y ( p ) � Fault modeling (Chapter 4) Sharif University of Technology Digital Testing: Chapter 1 Slide 4 of 18
Course Outline (Cont.) Course Outline (Cont.) Part II: Test Methods � Logic and fault simulation (Chapter 5) � Testability measures (Chapter 6) � Combinational circuit ATPG (Chapter 7) � Sequential circuit ATPG (Chapter 8) � Memory test (Chapter 9) � Analog test (Chapters 10 and 11) � Delay test and IDDQ test (Chapters 12 and 13) Sharif University of Technology Digital Testing: Chapter 1 Slide 5 of 18
Course Outline (Cont.) Part III: DFT � Scan design (Chapter 14) � BIST (Chapter 15) � Boundary scan and analog test bus (Chapters 16 and 17) � System test and core-based design (Chapter 18) Sharif University of Technology Digital Testing: Chapter 1 Slide 6 of 18
Logistics � Class webpage: http://sharif.edu/~hessabi/test/index.html � Handouts: � Handouts: � Available at class webpage (in pdf format) � Class mailing list: Class mailing list: � Please enter your email address in “edu” system. Email messages will be sent to the list. Sharif University of Technology Digital Testing: Chapter 1 Slide 7 of 18
VLSI Realization Process VLSI Realization Process Customer’s need Customer’s need Deter Determine r ine requir quirements ments Write specifica ite specifications tions Design synthesis and V Design synthesis and Verifica Design synthesis and V Design synthesis and Verifica rification rification tion tion Test de st development lopment Fabrica brication ion Manufacturing test Man Manufacturing test Man facturing test facturing test Chi Chips to customer p s to customer Sharif University of Technology Digital Testing: Chapter 1 Slide 8 of 18
Definitions � Design synthesis: Given an I/O function, develop a procedure to manufacture a device using known materials and processes. � Verification: Predictive analysis to ensure that the synthesized design, when manufactured, will perform the given I/O function the given I/O function. � Test: A manufacturing step that ensures that the physical device manufactured from the synthesized physical device, manufactured from the synthesized design, has no manufacturing defect. Sharif University of Technology Digital Testing: Chapter 1 Slide 9 of 18
Verification versus Test � Verifies correctness of � Verifies correctness of � Verifies correctness of manufactured hardware. design. � Two-part process: � Performed by simulation, p p y , � 1. Test generation: software hardware emulation, or process executed once during formal methods. design design � 2. Test application: electrical tests applied to hardware � Performed once prior to � P f d i t � Test application performed on manufacturing. every manufactured device. � Responsible for quality � Responsible for quality � Responsible for quality of of design. devices. Sharif University of Technology Digital Testing: Chapter 1 Slide 10 of 18
Ideal Tests � Ideal tests: � Detect all defects produced in the manufacturing process � Detect all defects produced in the manufacturing process. � Pass all functionally good devices. � Problems: Problems: � Very large numbers and varieties of possible defects need to be tested. � Difficult to generate tests for some real defects. � Defect-oriented testing is an open problem. Sharif University of Technology Digital Testing: Chapter 1 Slide 11 of 18
Real Tests � Based on analyzable fault models, which may not map on real defects. l d f t � Incomplete coverage of modeled faults due to high complexity complexity. � Some good chips are rejected. � Yield loss : fraction (or percentage) of such chips � Yield loss : fraction (or percentage) of such chips . � Some bad chips pass tests. � Defect level : fraction (or percentage) of bad chips among all � Defect level : fraction (or percentage) of bad chips among all passing chips. Sharif University of Technology Digital Testing: Chapter 1 Slide 12 of 18
Testing as Filter Process Testing as Filter Process Mostly Mostl Good c Good chips ips Pr Prob(pass test) = ob(pass test) = high high go good Prob(g Pr Pr Prob(g ob(good) = ob(good) = ood) = y ood) = y ch chips Tested Fabricated chips chips Mostl Mostly Def Defectiv ective c e chips ips bad bad bad bad Prob(bad) = Pr ob(bad) = 1- 1- y Pr Prob(fail test) = ob(fail test) = high high ch chips Sharif University of Technology Digital Testing: Chapter 1 Slide 13 of 18
Costs of Testing � Design for testability (DFT) � Chip area overhead and yield reduction � Performance overhead � Software processes of test f f � Test generation and fault simulation � Test programming and debugging � Test programming and debugging � Manufacturing test � Automatic test equipment (ATE) capital cost � Automatic test equipment (ATE) capital cost � Test center operational cost Sharif University of Technology Digital Testing: Chapter 1 Slide 14 of 18
Design for Testability (DFT) es g o es ab y ( ) DFT refers to hardware design styles or added hardware that reduce test generation complexity. d t t ti l it Motivation: Test generation complexity increases exponentially with the size of the circuit. with the size of the circuit. Example: Test hardware applies tests to blocks A and B and to internal bus; avoids test generation for combined A and B blocks. Int. Int. bus Logic Logic PO PO PI PI block A block B Test Test output p input p Sharif University of Technology Digital Testing: Chapter 1 Slide 15 of 18
Cost of Manufacturing Testing in 2000AD g g � 0.5-1.0GHz, analog instruments, 1024 digital pins: ATE purchase price h i = $1.2M + 1,024 x $3,000 = $4.272M � Running cost (five year linear depreciation) � Running cost (five-year linear depreciation) = Depreciation + Maintenance + Operation = $0.854M + $0.085M + $0.5M $0.854M + $0.085M + $0.5M = $1.439M/year � Test cost (24 hour ATE operation) ( p ) = $1.439M/(365 x 24 x 3,600) = 4.5 cents/second Sharif University of Technology Digital Testing: Chapter 1 Slide 16 of 18
Roles of Testing � Detection: Determination whether or not the device under test (DUT) has some faults. ( ) � Diagnosis: Identification of a specific fault that is present on DUT. � Device characterization: Determination and correction of errors in design and/or test procedure. � Failure mode analysis (FMA): Determination of manufacturing process errors that may have caused defects on the DUT defects on the DUT. � to improve yield Sharif University of Technology Digital Testing: Chapter 1 Slide 17 of 18
Importance of Testing � Moore’s Law results from decreasing feature size � from 10s of μ m to 10s of nm for transistors and wires � from 10s of μ m to 10s of nm for transistors and wires � Operating frequencies have increased from 100KHz to several GHz � Decreasing feature size increases probability of defects during manufacturing process � A single faulty transistor or wire results in faulty IC � Testing required to guarantee fault-free products � Rule of Ten: cost to detect faulty IC increases by an order R l f T t t d t t f lt IC i b d of magnitude as we move from: � device → PCB → system → field operation � device → PCB → system → field operation � Testing performed at all of these levels Sharif University of Technology Digital Testing: Chapter 1 Slide 18 of 18
Recommend
More recommend
