VLSI Testing Yield and Fault Modeling Virendra Singh Associate - - PowerPoint PPT Presentation

▶

Aug 31, 2022 225 likes •443 views

VLSI Testing Yield and Fault Modeling Virendra Singh Associate Professor Computer Architecture and Dependable Systems Lab Department of Electrical Engineering Indian Institute of Technology Bombay http://www.ee.iitb.ac.in/~viren/ E-mail:

SLIDE 1

CADSL

VLSI Testing

Yield and Fault Modeling

Virendra Singh

Associate Professor Computer Architecture and Dependable Systems Lab Department of Electrical Engineering Indian Institute of Technology Bombay

http://www.ee.iitb.ac.in/~viren/ E-mail: viren@ee.iitb.ac.in

Testing & Verification of VLSI Circuits

Lecture 5

SLIDE 2

CADSL

Costs of Testing

Design for testability (DFT)

– Chip area overhead and yield reduction – Performance overhead

Software processes of test

– Test generation and fault simulation – Test programming and debugging

Manufacturing test

– Automatic test equipment (ATE) capital cost – Test center operational cost

24 Jan 2013 EE-709@IITB 2

SLIDE 3

CADSL

Design for Testability (DFT)

DFT refers to hardware design styles or added hardware that reduces test generation complexity. Motivation: Test generation complexity increases exponentially with the size of the circuit. Logic block A Logic block B Primary inputs (PI) Primary

utputs

(PO) Test input Test

utput

Int. bus Example: Test hardware applies tests to blocks A and B and to internal bus; avoids test generation for combined A and B blocks.

24 Jan 2013 EE-709@IITB 3

SLIDE 4

CADSL

Testing Principle

24 Jan 2013 EE-709@IITB 4

SLIDE 5

CADSL

ADVANTEST Model T6682 ATE

24 Jan 2013 EE-709@IITB 5

SLIDE 6

CADSL

Cost of Manufacturing Testing

0.5-1.0GHz; analog instruments; 1,024 digital pins:

ATE purchase price = $1.2M + 1,024 x $3,000 = $4.272M

Running cost (five-year linear depreciation)

= Depreciation + Maintenance + Operation = $0.854M + $0.085M + $0.5M = $1.439M/year

Test cost (24 hour ATE operation)

= $1.439M/(365 x 24 x 3,600) = 4.5 cents/second

24 Jan 2013 EE-709@IITB 6

SLIDE 7

CADSL

Cost Analysis Graph

40,000 25,000 20,000 200k 150k 100k 50k 100 50 Miles Driven Fixed, Total and Variable Costs ($) Average Cost (cents) T

a l c

t Fixed cost Variable cost Average cost

24 Jan 2013 EE-709@IITB 7

SLIDE 8

CADSL

A Modern VLSI Device System-on-a-chip (SOC)

DSP core RAM ROM Inter- face logic Mixed- signal Codec Data terminal Transmission medium

24 Jan 2013 EE-709@IITB 8

SLIDE 9

CADSL

VLSI Chip Yield

A manufacturing defect is a finite chip area with electrically malfunctioning circuitry caused by errors in the fabrication process. A chip with no manufacturing defect is called a good chip. Fraction (or percentage) of good chips produced in a manufacturing process is called the yield. Yield is denoted by symbol Y. Cost of a chip:

Cost of fabricating and testing a wafer

Yield x Number of chip sites on the wafer

24 Jan 2013 EE-709@IITB 9

SLIDE 10

CADSL

Clustered VLSI Defects

Wafer Defects Faulty chips Good chips Unclustered defects Wafer yield = 12/22 = 0.55 Clustered defects (VLSI) Wafer yield = 17/22 = 0.77

24 Jan 2013 EE-709@IITB 10

SLIDE 11

CADSL

Yield Parameters

Defect density (d ) = Average number of defects per

unit of chip area

Chip area (A)
Clustering parameter (α)
Negative binomial distribution of defects,

p (x ) = Prob (number of defects on a chip = x )

Γ (α+x ) (Ad /α) x

= ------------- . ---------------------- x ! Γ (α) (1+Ad /α) α+x where Γ is the gamma function α = 0, p (x ) is a delta function (maximum clustering) α = ∞ , p (x ) is Poisson distribution (no clustering)

24 Jan 2013 EE-709@IITB

SLIDE 12

CADSL

Yield Equation

Y = Prob ( zero defect on a chip ) = p (0) Y = ( 1 + Ad / α ) − α Example: Ad = 1.0, α = 0.5, Y = 0.58 Unclustered defects: α = ∞, Y = e - Ad Example: Ad = 1.0, α = ∞, Y = 0.37 too pessimistic !

24 Jan 2013 EE-709@IITB

SLIDE 13

CADSL

Defect Level or Reject Ratio

 Defect level (DL) is the ratio of faulty chips

among the chips that pass tests.

 DL is measured as parts per million (ppm).  DL is a measure of the effectiveness of tests.  DL is a quantitative measure of the

manufactured product quality. For commercial VLSI chips a DL greater than 500 ppm is considered unacceptable.

24 Jan 2013 EE-709@IITB

SLIDE 14

CADSL

Determination of DL

 From field return data: Chips failing in the field

are returned to the manufacturer. The number

f returned chips normalized to one million chips

shipped is the DL.

 From test data: Fault coverage of tests and chip

fallout rate are analyzed. A modified yield model is fitted to the fallout data to estimate the DL.

24 Jan 2013 EE-709@IITB

SLIDE 15

CADSL

Modified Yield Equation

Three parameters:
Fault density, f = average number of

stuck-at faults per unit chip area

Fault clustering parameter, β
Stuck-at fault coverage, T
The modified yield equation:

Y (T ) = (1 + TAf / β) - β Assuming that tests with 100% fault coverage (T =1.0) remove all faulty chips, Y = Y (1) = (1 + Af / β) - β

24 Jan 2013 EE-709@IITB

SLIDE 16

CADSL

Defect Level

Y (T ) - Y (1) DL (T ) = -------------------- Y (T ) ( β + TAf ) β = 1 - -------------------- ( β + Af ) β Where T is the fault coverage of tests, Af is the average number of faults on the chip of area A, β is the fault clustering parameter. Af and β are determined by test data analysis.

24 Jan 2013 EE-709@IITB

SLIDE 17

CADSL

5 1 0 1 5 2 0 2 5 3 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 1 0 0 F a u l t C o v e r a g e D e f e c t L e v e l

Yield and Fault Coverage

24 Jan 2013 EE-709@IITB

SLIDE 18

CADSL

Computed DL

Stuck-at fault coverage (%) Defect level in ppm 237,700 ppm (Y = 76.23%)

SEMATECH Chip (Courtesy: IBM)

24 Jan 2013 EE-709@IITB

SLIDE 19

CADSL

T i m e i n M

n t h s

R e v e n u e s

∆ T

T i m e t o M a r k e t L o s s o f R e v e n u e s

Time to Market

24 Jan 2013 EE-709@IITB

SLIDE 20

CADSL

Failure Rate Vs Product Lifetime

24 Jan 2013 EE-709@IITB