Optimizing and Comparing CMOS Implementations of the C-element - PowerPoint PPT Presentation

Optimizing and Comparing CMOS Implementations of the C-element in 65nm Technology: Self-Timed Ring Case Oussama Elissati 1,2 , Eslam Yahya 1,3 , Sébastien Rieubon 2 , Laurent Fesquet 1 1 TIMA Lab. – CIS Group, Grenoble, France 2 ST-Ericsson, Grenoble, France 3 Higher Institute of Technology, Banha, Egypt 28/09/2010 1 CNRS - Grenoble-INP - UJF

Oscillators and VCO Oscillators are mandatory for : • Generating the clock synchronization signal. • Modulating and demodulating signals. • Retrieving signals in noise. • Communication applications : � Phase-Locked Loops (PLL) with strong requirements on stability, phase noise and power consumption. 28/09/2010 28/09/2010 2 2 PATMOS 2010, Grenoble O.Elissati et al.

Self-Timed Ring Oscillators •Well-suited characteristics for managing process variability [Hamon 08] •Considered as promising solution for generating clocks. [Fairbanks 04] •Generating High-speed Multi-phase Clocks. [Elissati 10] •Offering an appropriate structure to limit the phase noise.[Elissati 10] 28/09/2010 28/09/2010 3 3 PATMOS 2010, Grenoble O.Elissati et al.

Outlines 1 Self-Timed Rings 2 C-element Implementations 3 Design of the ring stages 4 Simulation results 5 Conclusion 28/09/2010 28/09/2010 4 4 PATMOS 2010, Grenoble O.Elissati et al.

Self-Timed Ring D ff 0 1 1 1 T B T T B C C C C 0 D rr •Tokens and bubbles •Propagation rules { } = ⇒ = C C Stage Bubble + ⎯ ⎯⎯ → i i 1 i token ⇔ ≠ = ← ⎯⎯ ⎯ Stage Stage C C C − − + { } i 1 i ( i 1)% L i ( i 1)% L bubble ≠ ⇒ = C C Stage Token + i i 1 i 28/09/2010 28/09/2010 6 6 PATMOS 2010, Grenoble O.Elissati et al.

Self-Timed Ring The frequency depends on the initialization 1 = F + OSC 2. D .(R 1) ( ) ≥ ⎧ D , N N if D D N N ( ) = rr T B ff rr T B ⎨ D, R ( ) ≤ ⎩ D , N N if D D N N ff B T ff rr T B = The maximal frequency is reached when D D N N ff rr T B 28/09/2010 28/09/2010 7 7 PATMOS 2010, Grenoble O.Elissati et al.

C-element implementations Dynamic & Weak feed-back Dynamic Weak feed-back [Martin 89] 28/09/2010 28/09/2010 9 9 PATMOS 2010, Grenoble O.Elissati et al.

C-element implementations Conventional & Symmetric Symmetric [Berkel 94] Conventional [Sutherland 89] 28/09/2010 28/09/2010 10 10 PATMOS 2010, Grenoble O.Elissati et al.

Design of the ring stages Logical effort* *From [Sutherland 99] •Optimize the stage speed (Logical, Electrical and Branching efforts) •The optimization of speed contribute to the phase noise reduction. F R U1=0.89 U2=0.56 F γ ⋅ W n γ ⋅ ⋅ γ ⋅ ⋅ γ ⋅ W U W U W 1 n 2 n n R Cout =C R +C F U ⋅ W U ⋅ W W n 2 n 1 n W n 28/09/2010 12 12 PATMOS 2010, Grenoble O.Elissati et al.

Design of the ring stages Electrical simulations U2 U1 2T/3B conventional implementation Same figure shape whatever the implementation, the initialisation and the power consumption 28/09/2010 28/09/2010 13 13 PATMOS 2010, Grenoble O.Elissati et al.

Design of the ring stages Comparaison Optimal frequency Ring (conventional) Logical effort U 1 U 2 U1=0.89 3 stages 1B/2T 1 0.9 U2=0.56 4 stages 2B/2T 1 0.9 5 stages 1B/4T 1 0.9 5 stages 3B/2T 0.9 0.5 28/09/2010 28/09/2010 14 14 PATMOS 2010, Grenoble O.Elissati et al.

Simulation results Frequency vs. Power Power 2T/3B U1 et U2 optimal 28/09/2010 28/09/2010 16 16 PATMOS 2010, Grenoble O.Elissati et al.

Simulation results Figure of Merit (FOM) ⎛ ⎞ ⎛ ⎞ f P ⎜ ⎟ = − + ⎜ ⎟ 0 s FOM L ( f ) 20 log 10 log ⎜ ⎟ m ⎝ ⎠ ⎝ ⎠ f 1 mW m 28/09/2010 28/09/2010 17 17 PATMOS 2010, Grenoble O.Elissati et al.

Conclusions •A C-element implementation comparison in terms of: speed, power and phase noise. What to keep in mind: •For high speed, low-power applications: use dymanic or symmetric •For small area and low frequency: use conventional or weak feedback •For low-phase noise applications: avoid the weak feedback, prefer the conventional 28/09/2010 28/09/2010 19 PATMOS 2010, Grenoble O.Elissati et al.

References [Fairbanks 04] S. Fairbanks and S. Moore, “Analog micropipeline rings for high precision timing”, ASYNC’04, CRETE, Greece, IEEE, April 2004, pp. 41–50. [Hamon 08] J. Hamon, L. Fesquet, B. Miscopein and M. Renaudin “High-Level Time-Accurate Model for the Design of Self-Timed Ring Oscillators”, ASYNC’08, Newcastle, UK, IEEE, April 2008, pp. 29-38. [Elissati 00] O. Elissati, E. Yahya, S. Rieubon, L. Fesquet “High-Speed High_Resolution Low-Phase Noise Oscillator using Self-Timed Rings ”, IEEE/IFIP VLSI-SOC’2010, Septembre 27-29, 2010, Madrid, Spain. [Martin 89] A. J. Martin, “Formal progress transformations for VLSI circuit synthesis,” in Formal Development of Programs and Proofs E. W. Dijkstra, Ed. Reading, MA: Addison-Wesley, 1989, pp. 59–80. [Sutherland 89] I. E. Sutherland, “Micropipelines,” Commun. ACM, vol. 32, pp.720–738, June 1989. [Berkel 94] K. v. Berkel, R. Burgess, J. Kessels, A. Peeters, M. Roncken, and F.Schalij, “A fully-asynchronous low-power error corrector for the DCC player,” IEEE J. Solid-State Circuits, vol. 29, pp. 1429–1439, Dec. 1994. [Sutherland 99] I. Sutherland, B. Sproull, and D. Harris, Logical Effort: Designing Fast CMOS Circuits. San Fransisco, CA: Morgan Kaufmann, 1999. 28/09/2010 28/09/2010 20 PATMOS 2010, Grenoble O.Elissati et al.

Performances comparison Phase noise 28/09/2010 28/09/2010 21 PATMOS 2010, Grenoble O.Elissati et al.

Optimizing and Comparing CMOS Implementations of the C-element - PowerPoint PPT Presentation

Optimizing and Comparing CMOS Implementations of the C-element in 65nm Technology: Self-Timed Ring Case Oussama Elissati 1,2 , Eslam Yahya 1,3 , Sbastien Rieubon 2 , Laurent Fesquet 1 1 TIMA Lab. CIS Group, Grenoble, France 2

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Optimizing and Comparing CMOS Implementations of the C-element - PowerPoint PPT Presentation

Optimizing and Comparing CMOS Implementations of the C-element in 65nm Technology: Self-Timed Ring Case Oussama Elissati 1,2 , Eslam Yahya 1,3 , Sbastien Rieubon 2 , Laurent Fesquet 1 1 TIMA Lab. CIS Group, Grenoble, France 2

Outline Architectures for CMOS EDC Linear equalizer implementations Feedback

Optimizing Implementations of Linear Layers Zejun Xiang, Xiangyong Zeng, Da Lin, Zhenzhen Bao,

Comparing 2 implementations of the IETF-IPPM One-Way Delay and Loss Metrics Sunil Kalidindi,

Outline A Brief History CMOS Gate Design Pass Transistors CMOS Latches &amp;

CMOS technologies in the 1 0 0 nm range CMOS technologies in the 1 0 0 nm range for rad-hard

UMBC A B M A L T F O U M B C I M Y O R T 1 (November 27, 2000 6:34 pm) I E S

Integration, Architecture, and Applications of 3D CMOS Memristor Circuits K. T. Tim Cheng

Working Around the Limits of Working Around the Limits of CMOS CMOS CMOS CMOS Mary Jane

Threshold Implementations Svetla Nikova Threshold Implementations A provably secure

Modeling Frequency Response of 65 nm CMOS RF Power Devices CMOS RF P D i i 1 J Usha Gogineni 1

CMOS Image Sensor Simulation 2D and 3D Simulation Basic Structure and operation of CMOS Image

CMOS Inverter Two Inverters N Well VDD Share power and ground V DD PMOS is wider Abut cells

A Novel DPS Integrator for Fast CMOS Imagers J. M. Margarit, J. Sabadell, L. Ters and F.

ASIC Physical Design CMOS Processes Smith Text: Chapters 2 &amp; 3 Weste CMOS VLSI

Comparing Several Samples We are often interested in comparing measurements made under more than

CMOS Inverter: Power Dissipation and Sizing CMOS Inverter Power Dissipation Professor Chris H.

Concepts of programming languages Lecture 6 Wouter Swierstra Faculty of Science Information and

1 How gates work NOT ( ) NAND ( ) o Transistors can be made to

263-2810: Advanced Compiler Design 8.2 Scheduling for ILP processors Thomas R. Gross Computer

Towards a Reconfigurable Bit-Serial/Bit-Parallel Vector Accelerator Using In-Situ

Chapter Five 1 2004 Morgan Kaufmann Publishers The Processor: Datapath &amp; Control

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Pipeline Hazards Again Computer System Architecture I-Fet ch DCD MemOpFetch OpFetch

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