[PPT] - In SOI technology M. Battaglia 1,2 , D. Bisello 3 , D. Contarato 2 , PowerPoint Presentation

SLIDE 1

M. Battaglia1,2, D. Bisello3, D. Contarato2, P. Denes2, P. Giubilato2,3,
S. Mattiazzo3, D. Pantano3, N. Pozzobon3, M. Tessaro3

1University of California at Berkeley, Berkeley, CA, USA 2Lawrence Berkeley National Laboratory, Berkeley, CA, USA 3University of Padova & INFN Padova, Padova, IT, EU

Monolithic Active Pixel Sensor In SOI technology

SLIDE 2

2/19 Hiroshima 2009 - Piero Giubilato –MAPS in SOI technology

SOI Silicon on Insulator

SOI technology integrates CMOS electronics on top of a Buried Oxide (SOI), ensuring full dielectric isolation, small

active volume and low junction capacitance: latch-up immune, low power, high speed designs are thus favoured

0.15-0.20 µm Fully-Depleted (FD) SOI processes from OKI, Japan allow contacting a high-resistivity (700 Ω/cm)

substrate through the BOX for pixel implanting and substrate reverse bias

Possibility for small pitch pixel sensors with high density, full CMOS readout electronics integrated in the same

device → SOI Monolithic Pixel Sensors

Functionality demonstrated by prototype chip from KEK in 2006; subsequent runs in 2007-2009 including LBNL

designs with analog and binary pixel architectures

40 nm silicon layer isolated from the bulk by the SiO2 layer - > No PNPN parasitic structs. Small charge generation into the active area of the transistor, lower sensitivity to SEE.

SLIDE 3

3/19 Hiroshima 2009 - Piero Giubilato –MAPS in SOI technology

OKI SOI process

Gate BOX Metal Metal Metal 1µm

Process: OKI 0.15m fully-depleted SOI CMOS process, 1 Poly, 5 Metal SOI wafer: Wafer Diameter: 150 mm, Top Si : Cz, ~18 -cm, p-type, 40 nm thick fully depleted Buried Oxide: 200 nm thick Handle wafer: Cz 700 -cm, 650 m thick (SOITEC ion cut) Backside: Thinned to 350 m, plated with Al (200 nm).

OKI 0.15 µm SOI process

SLIDE 4

4/19 Hiroshima 2009 - Piero Giubilato –MAPS in SOI technology

The high field in the depleted substrate causes back- gating of the CMOS electronics on top of the BOX Test of single transistors vs. depletion voltage: shift in the threshold voltage with increasing substrate voltage Significant effect observed in single transistor tests: expect analog section functional only for Vdep < 20 V Floating pguard structures around each pixel to keep potential low and limit back-gate effects on MOSFETs

VCI2007 T. Tsuboyama The threshold voltage of FETs is calculated with a guard ring at distance of 2, 5 and 80 μm. At 2 μm, the threshold shift can be suppressed to 0.1 V at bias voltage of 100 V.

Back-gating effect

SLIDE 5

5/19 Hiroshima 2009 - Piero Giubilato –MAPS in SOI technology

LDRD SOI 01

OKI 0.15 µm FD-SOI process, 160x150 pixels, 10 µm pitch
2 analog sections: 1.8 V and 1.0 V 3-transistor (3T) pixels
1 digital section: in-pixel comparator and latch, no amplifier

(very low power dissipation), adjustable threshold → 15 transistors/pixel

Floating p-type guard-ring around each pixel to limit back-

gating of the CMOS electronics due to electrostatic field in the substrate Analog pixels Digital pixels

LDRD-SOI-1

Clocked comparator with common voltage threshold

SLIDE 6

6/19 Hiroshima 2009 - Piero Giubilato –MAPS in SOI technology

LDRD SOI 01 – Analog pixels results

1.35 GeV e- LBNL ALS [M. Battaglia et al., NIM A 583 (2007) 526] [M. Battaglia et al., NIM A 604 (2009) 380]

Depletion region thickness vs substrate voltage

measured with focused 1060 nm laser

Expect signal proportional to depletion region

thickness D

Good agreement with expectation for Vdep~10V

(D~45 mm), back-gating effects becoming significant for larger voltages

Sensor spatial resolution studied by means of pixel

scans performed on the analog pixels with 1060 nm laser focused to a 5 um spot for different S/N values

With pixels of 10 um pitch, 1 um single point

resolution is achievable for a S/N ratio of 20

SLIDE 7

7/19 Hiroshima 2009 - Piero Giubilato –MAPS in SOI technology

LDRD SOI 01 – Analog pixels results

1.35 GeV e- LBNL ALS [M. Battaglia et al., NIM A 583 (2007) 526] [M. Battaglia et al., NIM A 604 (2009) 380]

1.35 GeV e-beam extracted from the injection

booster at the LBNL Advanced Light Source

First successful high momentum particle beam test
n SOI monolithic pixel sensors
As a function of the increasing Vdep: cluster pulse

height increases and cluster multiplicity decreases, up to Vdep~10 V, consistent with lab tests and back-gating effects becoming important at Vdep=10 V

Vdep Cl/Event [Beam] Cl/Event [No beam] Signal MPV [ADC count] AVG S/N 1 3.9 0.02 105 7.4 5 6.7 0.03 140 8.8 10 4.4 0.03 164 8.1 15 1.4 0.02 123 6.5

1.8 V analog pixels, Vdep = 10 V

SLIDE 8

8/19 Hiroshima 2009 - Piero Giubilato –MAPS in SOI technology

LDRD SOI 01 – Digital pixels results

[M. Battaglia et al., NIM A 583 (2007) 526] [M. Battaglia et al., NIM A 604 (2009) 380]

Adjustable integration time: reduced problem of

charge loss due to leakage current

Signal above threshold only at high substrate

voltages: ➢ analog threshold affected by back-gating ➢ larger depletion -> increased charge signal ➢ at 25-30 V, these effects seem to combine for best detection capabilities

Cluster multiplicity decreases with increasing Vdep

Vdep Cl/Event [Beam] Cl/Event [No beam] Px/Cluster 20 3.62 0.04 11300 25 5.81 0.04 71400 30 8.31 0.04 50 35 1.60 0.01 70

SLIDE 9

9/19 Hiroshima 2009 - Piero Giubilato –MAPS in SOI technology

LSRD SOI 02

OKI 0.20 µm FD-SOI process, optimized for low leakage current
5x5 mm2 prototype, 20x20 µm2 pixels, 1.8 V operational voltage
40x172 analog pixels, 3T architecture
128x172 binary pixels: 2 capacitors for in-pixel CDS, clocked comparator

with current threshold → 40 transistors/pixel

Up to 50 MHz readout, multiple (25) parallel digital outputs for improved

frame rate

LDRD-SOI-2

Analog pixels Digital pixels

Clocked comparator with current threshod Clocked current amplifier

SLIDE 10

10/19 Hiroshima 2009 - Piero Giubilato –MAPS in SOI technology

LDRD SOI 02 – Analog Pixels test on 1.5 GeV e- Vdep = 2 V Cluster signal vs Vdep

Analog pixels tested with 1.5 GeV electrons at LBNL

ALS with 50 MHz readout, achieving S/N~20 and ENC~ 20-30 e-

Stronger effect of back-gating compared to 0.15 µm

process; detector properly operable up to Vdep~5 V

SLIDE 11

11/19 Hiroshima 2009 - Piero Giubilato –MAPS in SOI technology

LDRD SOI 02 – Analog Pixels test on 1.5 GeV e-

Cluster size behaves as expected respect the applied

depletion voltage

The pixel works fine up to 50 MHz frequency

Vdep = 2 V

SLIDE 12

12/19 Hiroshima 2009 - Piero Giubilato –MAPS in SOI technology

LDRD SOI 2- Digital Pixels test Dark noise (S curve)

[NOTE: Ithresh is inversely proportional to pixel threshold in S/N]

90Sr measurements

Digital pixels tested with 90Sr source: current

threshold affected by back-gating but 90Sr hits visible up to Vdep = 35 V Vdep = 35 V Ithresh = 125 µA

S-curve have been measured for various depletion
voltages. Threshold dispersion increases with Vdep.

SLIDE 13

13/19 Hiroshima 2009 - Piero Giubilato –MAPS in SOI technology

Open R&D Issues

Optmization of substrate field: define optimum biasing configuration → TCAD simulations under way
Back-gating, especially at peripheral region (I/O electronics): define optimum guard-ring configuration →

TCAD simulations

Radiation hardness: build-up of charge in the BOX increases the effect of back-gating; non-ionizing

radiation shown to increase leakage

29 MeV proton irradiation ~600 krad

increasing Vdep

Thinning and back-processing, e.g. δ-doping from JPL/NASA: deposit 1-2 atomic layers of p dopant at the

back-side; thin entrance window for improved VUV efficiency. Possibility for fully-depleted, back- illuminated sensor for soft X-ray detection

SLIDE 14

14/19 Hiroshima 2009 - Piero Giubilato –MAPS in SOI technology

Radiation hardness studies

increasing Vdep

n-MOSFET W/L=50/0.3

In SOI technology, the thick buried oxide is expected to be sensitive to ionizing doses, which lead to

positive charge trapping and consequently to an increase of the top-gate leakage current.

This effect is even larger for depleted structures: the strong electrical field across the BOX splits the

electron-holes pair generated by ionizing radiation, reducing the recombination yield. This greatly increases the amount positive charge which is trapped throughout the BOX. The number of electron- hole pairs escaping recombination (“fractional yield”) hence strongly depends on the bias given to the substrate. It also depends on the stopping power of the incident particle (the lower the ionization density, the lower the recombination probability).

SLIDE 15

15/19 Hiroshima 2009 - Piero Giubilato –MAPS in SOI technology

Radiation hardness studies

increasing Vdep

n-MOSFET W/L=50/0.3

For NMOS test structures there is a huge difference when the transistor is irradiated with no depletion

voltage and a depletion voltage of 10 V.

Transistor have been irradiated in ON status (Gate HIGH) and with p substrate floating.

Ids-Vgs curve for the M5 NMOS transistor before and after irradiation at Vback = 0V

M5 NMOS (Vback = 10V)

1.E-12 1.E-11 1.E-10 1.E-09 1.E-08 1.E-07 1.E-06 1.E-05 1.E-04 1.E-03 1.E-02 1.E-01 1.E+00

0.2

0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8

Vgs (V) Ids (A) pre 5 krad 13 krad 18 krad 23 krad 28 krad 33 krad 38 krad 43 krad 48 krad M5 NMOS (Vback = 0V)

1.E-12 1.E-11 1.E-10 1.E-09 1.E-08 1.E-07 1.E-06 1.E-05 1.E-04 1.E-03 1.E-02 1.E-01 1.E+00

0.2

0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8

Vgs (V) Ids (A) pre 30 krad 45 krad 80 krad 120 krad 170 krad 240 krad 380 krad 1.1 Mrad 2 Mrad

L = 0.5um, W = 250um, no body tie, low Vtht

SLIDE 16

16/19 Hiroshima 2009 - Piero Giubilato –MAPS in SOI technology

M13 NMOS (Vback = 10V)

1.E-12 1.E-11 1.E-10 1.E-09 1.E-08 1.E-07 1.E-06 1.E-05 1.E-04 1.E-03 1.E-02 1.E-01 1.E+00

0.2

0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8

Vgs (V) Ids (A) pre 13 krad 18 krad 28 krad 33 krad 38 krad 43 krad 48 krad 55 krad 62 krad

Radiation hardness studies

increasing Vdep

n-MOSFET W/L=50/0.3

Different transistor type (with connected body, non low threshold) did show promising radiation tolerance
Transistor have been irradited in ON status (Gate HIGH) and with p substrate floating.

Ids-Vgs curve for the M5 NMOS transistor before and after irradiation at Vback = 0V

L = 0.5um, W = 250um, body tie, normal Vtht

M13 NMOS (Vback = 0V)

1.E-12 1.E-11 1.E-10 1.E-09 1.E-08 1.E-07 1.E-06 1.E-05 1.E-04 1.E-03 1.E-02 1.E-01 1.E+00

0.2

0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8

Vgs (V) Ids (A) pre 10 krad 30 krad 60 krad 100 krad 200 krad 300 krad 680 krad 1.1 Mrad 2 Mrad

SLIDE 17

17/19 Hiroshima 2009 - Piero Giubilato –MAPS in SOI technology

By irradiating the transistors with Vdep = 0, the

normal threshold one shows good tolerance to ionizing radiation.

Radiation hardness: promising results

increasing Vdep

n-MOSFET W/L=50/0.3

Ids-Vgs curve for the M5 NMOS transistor before and after irradiation at Vback = 0V

M13 NMOS leakage

1.E-12 1.E-11 1.E-10 1.E-09 1.E-08 1.E-07 1.E-06 1.E-05 1.E-04 1.E-03 1.E-02 1 10 100 1000 10000

Dose (krad) Ileak (A) 0V 5V 10V

We found that by keeping the p substrate ring to 0

V, the back-gate effect is greatly reduced.

M2 NMOS; PSUB floating

1.E-12 1.E-10 1.E-08 1.E-06 1.E-04 1.E-02 1.E+00

0.2

0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8

Vgs (V) Ids (A) Vback = 0V Vback = 2V Vback = 4V Vback = 6V Vback = 8V Vback = 10V Vback = 12V Vback = 15V M2 NMOS; PSUB at GND

1.E-12 1.E-10 1.E-08 1.E-06 1.E-04 1.E-02 1.E+00

0.2

0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 Vgs (V) Ids (A) Vback = 0V Vback = 2V Vback = 4V Vback = 6V Vback = 8V Vback = 10V Vback = 12V Vback = 15V

Next step: irradiating a depleted transistor while

keeping the p guard ring tied to 0 V, results should be promising!

SLIDE 18

18/19 Hiroshima 2009 - Piero Giubilato –MAPS in SOI technology

SOI Imager SOI 3D

OKI 0.20 µm FD-SOI process
5x5 mm2 area, 256x256 analog pixels, 13.75 µm

pitch

4 parallel analog outputs, readout at 50 MHz, ~2-3

kframes/sec

Plans for thinning and back-processing with δ-

doping (collaboration with JPL/NASA)

Build tracker prototype for high resolution (~1.5 µm)

tracking studies

OKI 0.20 µm FD-SOI process
Sensor chip with graded p-type guard-rings
Readout chip to be wafer-bonded on top by ZyCube

process

256x256 analog pixels, 13.75 µm pitch, 8 different

pixel types, several test structures for process and interconnection evaluation

Bottom chip (sensor) Top chip (readout)

SLIDE 19

19/19 Hiroshima 2009 - Piero Giubilato –MAPS in SOI technology

Conclusions

SOICMOS technology built on high resistivity substrates allows the fabrication of reversely biased silicon

sensors integrated with full CMOS circuitry on the same device

LDRDSOI1 prototype in 0.15 um process successfully tested:

Analog and digital pixel detection capabilities demonstrated with IR laser and 1.35 GeV e- Back-gating effects significant at high substrate voltages and after irradiation with protons

LDRDSOI2 fabricated in optimized (low leak) 0.20 um process:

Extremely good uniformity and noise performance for the analog pixels Back-gating still a problem, more R&D needed to address the problem Promising results hint for good (anyway not tracker level) radiation hardness of the technology

Two new chip just arrived from the foundry: an all analog IMAGER optimized for high speed, and a 3D one

to test the ZyCube process, which should deliver good radiation hardness.

Several potential technology spinoffs for SOI monolithic pixels:

Thin, fast and integrated detectors for High Energy Physics applications Xray detection for application at synchrotron facilities VUV imaging for beam diagnostics, e.g. via thinning and backprocessing