In SOI technology M. Battaglia 1,2 , D. Bisello 3 , D. Contarato 2 , - PowerPoint PPT Presentation

Monolithic Active Pixel Sensor In SOI technology M. Battaglia 1,2 , D. Bisello 3 , D. Contarato 2 , P. Denes 2 , P. Giubilato 2,3 , S. Mattiazzo 3 , D. Pantano 3 , N. Pozzobon 3 , M. Tessaro 3 1 University of California at Berkeley, Berkeley, CA, USA 2 Lawrence Berkeley National Laboratory, Berkeley, CA, USA 3 University of Padova & INFN Padova, Padova, IT, EU

SOI Silicon on Insulator ● SOI technology integrates CMOS electronics on top of a Buried Oxide (SOI), ensuring full dielectric isolation, small active volume and low junction capacitance: latch-up immune, low power, high speed designs are thus favoured ● 0.15-0.20 µm Fully-Depleted (FD) SOI processes from OKI, Japan allow contacting a high-resistivity (700 Ω /cm) substrate through the BOX for pixel implanting and substrate reverse bias ● Possibility for small pitch pixel sensors with high density, full CMOS readout electronics integrated in the same device → SOI Monolithic Pixel Sensors ● Functionality demonstrated by prototype chip from KEK in 2006; subsequent runs in 2007-2009 including LBNL designs with analog and binary pixel architectures Small charge generation into the 40 nm silicon layer isolated active area of the transistor, from the bulk by the SiO 2 layer - lower sensitivity to SEE. > No PNPN parasitic structs. 2/19 Hiroshima 2009 - Piero Giubilato – MAPS in SOI technology

OKI SOI process Metal OKI 0.15 µm SOI process 1µm OKI 0.15  m fully-depleted SOI CMOS process, 1 Poly, 5 Metal Process: Metal Buried Oxide: 200 nm thick Wafer Diameter: 150 mm, SOI Top Si : Cz, ~18  -cm, p-type, Handle wafer: Cz 700  -cm, 650 wafer:  m thick (SOITEC ion cut) 40 nm thick fully depleted Metal Gate BOX Thinned to 350  m, plated with Al (200 nm). Backside: 3/19 Hiroshima 2009 - Piero Giubilato – MAPS in SOI technology

Back-gating effect The high field in the depleted substrate causes back- gating of the CMOS electronics on top of the BOX Test of single transistors vs. depletion voltage: shift in the threshold voltage with increasing substrate voltage Significant effect observed in single transistor tests: expect analog section functional only for V dep < 20 V Floating pguard structures around each pixel to keep potential low and limit back-gate effects on MOSFETs VCI2007 T. Tsuboyama The threshold voltage of FETs is calculated with a guard ring at distance of 2, 5 and 80 μ m. At 2 μm , the threshold shift can be suppressed to 0.1 V at bias voltage of 100 V. 4/19 Hiroshima 2009 - Piero Giubilato – MAPS in SOI technology

LDRD SOI 01 ● OKI 0.15 µm FD-SOI process, 160x150 pixels, 10 µm pitch ● 2 analog sections: 1.8 V and 1.0 V 3-transistor (3T) pixels LDRD-SOI-1 ● 1 digital section: in-pixel comparator and latch, no amplifier (very low power dissipation), adjustable threshold → 15 transistors/pixel ● Floating p-type guard-ring around each pixel to limit back- gating of the CMOS electronics due to electrostatic field in the substrate Analog pixels Digital pixels Clocked comparator with 5/19 common voltage threshold Hiroshima 2009 - Piero Giubilato – MAPS in SOI technology

LDRD SOI 01 – Analog pixels results • Depletion region thickness vs substrate voltage • Sensor spatial resolution studied by means of pixel measured with focused 1060 nm laser scans performed on the analog pixels with 1060 nm laser focused to a 5 um spot for different S/N • Expect signal proportional to depletion region values thickness D • With pixels of 10 um pitch, 1 um single point • Good agreement with expectation for Vdep~10V resolution is achievable for a S/N ratio of 20 (D~45 mm), back-gating effects becoming 1.35 GeV e - significant for larger voltages LBNL ALS [M. Battaglia et al., NIM A 583 (2007) 526] [M. Battaglia et al., NIM A 604 (2009) 380] 6/19 Hiroshima 2009 - Piero Giubilato – MAPS in SOI technology

LDRD SOI 01 – Analog pixels results • 1.35 GeV e - beam extracted from the injection Cl/Event Cl/Event Signal MPV V dep AVG S/N booster at the LBNL Advanced Light Source [Beam] [No beam] [ADC count] • First successful high momentum particle beam test 1 3.9 0.02 105 7.4 on SOI monolithic pixel sensors 5 6.7 0.03 140 8.8 • As a function of the increasing Vdep: cluster pulse 10 4.4 0.03 164 8.1 height increases and cluster multiplicity decreases, up to Vdep~10 V, consistent with lab tests and 15 1.4 0.02 123 6.5 1.35 GeV e - back-gating effects becoming important at LBNL ALS Vdep=10 V 1.8 V analog pixels, V dep = 10 V [M. Battaglia et al., NIM A 583 (2007) 526] [M. Battaglia et al., NIM A 604 (2009) 380] 7/19 Hiroshima 2009 - Piero Giubilato – MAPS in SOI technology

LDRD SOI 01 – Digital pixels results • Adjustable integration time: reduced problem of charge loss due to leakage current • Signal above threshold only at high substrate voltages: ➢ analog threshold affected by back-gating ➢ larger depletion -> increased charge signal ➢ at 25-30 V, these effects seem to combine for best detection capabilities • Cluster multiplicity decreases with increasing V dep Cl/Event Cl/Event V dep Px/Cluster [Beam] [No beam] 20 3.62 0.04 11300 25 5.81 0.04 71400 30 8.31 0.04 50 35 1.60 0.01 70 [M. Battaglia et al., NIM A 583 (2007) 526] 8/19 Hiroshima 2009 - Piero Giubilato – MAPS in SOI technology [M. Battaglia et al., NIM A 604 (2009) 380]

LSRD SOI 02 ● OKI 0.20 µm FD-SOI process, optimized for low leakage current ● 5x5 mm 2 prototype, 20x20 µm 2 pixels, 1.8 V operational voltage LDRD-SOI-2 ● 40x172 analog pixels, 3T architecture ● 128x172 binary pixels: 2 capacitors for in-pixel CDS, clocked comparator with current threshold → 40 transistors/pixel ● Up to 50 MHz readout, multiple (25) parallel digital outputs for improved frame rate Analog pixels Digital pixels Clocked comparator Clocked current with current threshod amplifier 9/19 Hiroshima 2009 - Piero Giubilato – MAPS in SOI technology

LDRD SOI 02 – Analog Pixels test on 1.5 GeV e - ● Analog pixels tested with 1.5 GeV electrons at LBNL ● Stronger effect of back-gating compared to 0.15 µm ALS with 50 MHz readout, achieving S/N~20 and process; detector properly operable up to V dep ~5 V ENC~ 20-30 e - V dep = 2 V Cluster signal vs V dep 10/19 Hiroshima 2009 - Piero Giubilato – MAPS in SOI technology

LDRD SOI 02 – Analog Pixels test on 1.5 GeV e - ● Cluster size behaves as expected respect the applied ● The pixel works fine up to 50 MHz frequency depletion voltage V dep = 2 V 11/19 Hiroshima 2009 - Piero Giubilato – MAPS in SOI technology

LDRD SOI 2- Digital Pixels test ● S-curve have been measured for various depletion ● Digital pixels tested with 90 Sr source: current threshold affected by back-gating but 90 Sr hits visible voltages. Threshold dispersion increases with V dep . up to V dep = 35 V Dark noise (S curve) 90 Sr measurements V dep = 35 V I thresh = 125 µA [NOTE: I thresh is inversely proportional to pixel threshold in S/N] 12/19 Hiroshima 2009 - Piero Giubilato – MAPS in SOI technology

Open R&D Issues ● Optmization of substrate field: define optimum biasing configuration → TCAD simulations under way ● Back-gating, especially at peripheral region (I/O electronics): define optimum guard-ring configuration → TCAD simulations ● Radiation hardness: build-up of charge in the BOX increases the effect of back-gating; non-ionizing radiation shown to increase leakage increasing V dep 29 MeV proton irradiation ~600 krad ● Thinning and back-processing, e.g. δ -doping from JPL/NASA: deposit 1-2 atomic layers of p dopant at the back-side; thin entrance window for improved VUV efficiency. Possibility for fully-depleted, back- illuminated sensor for soft X-ray detection 13/19 Hiroshima 2009 - Piero Giubilato – MAPS in SOI technology

Radiation hardness studies • In SOI technology, the thick buried oxide is expected to be sensitive to ionizing doses, which lead to positive charge trapping and consequently to an increase of the top-gate leakage current. • This effect is even larger for depleted structures: the strong electrical field across the BOX splits the electron-holes pair generated by ionizing radiation, reducing the recombination yield. This greatly increases the amount positive charge which is trapped throughout the BOX. The number of electron- hole pairs escaping increasing V dep recombination (“fractional yield”) hence strongly n-MOSFET depends on the bias given W/L=50/0.3 to the substrate. It also depends on the stopping power of the incident particle (the lower the ionization density, the lower the recombination probability). 14/19 Hiroshima 2009 - Piero Giubilato – MAPS in SOI technology