Additionneurs Ultra Basse Tension en Technologie SOI 0,13 - - PowerPoint PPT Presentation

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Additionneurs Ultra Basse Tension en Technologie SOI 0,13µ Partiellement Désertée

Jean Philippe Blanc, Hélène Lhermet, Marc Belleville CEA LETI Département Systèmes pour l’Information et la Santé

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Outlines

Introduction SOI Dtmos & Floating Body 1bit Adder Circuit architecture & testability Tests results Conclusion

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Purpose of this study

SOI 0.13 technology based on partially depleted transistors Evaluation of DTMOS performances for low voltage digital applications

Design and simulation of a 32-bits adder at low voltage (0.25V to 0.5V) The adder-circuits studied use different transistor types :

• > floating body or DTMOS
• > high speed or low leakage

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SOI DTMOS

Dynamic Threshold MOS (DTMOS) :

SOI transistor of which the threshold voltage is dynamically controlled by connecting the body to the gate. interests for very low power applications: improved Ion/Ioff ratio no history effect drawbacks : larger gate capacitance larger area

Floating body transistor DTMOS transistor

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Mix architecture of the 1-bit adder

The architecture is a mix between conventional logic and transmission gates. 3 versions with low Vt MOS . floating bodies only . floating bodies and DTMOS . DTMOS only 1 version with high Vt MOS (DTMOS only)

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Layouts and photograph of Adders

Adder with DTMOS only Area : 170 mm2 Adder with FB and DTMOS Area : 90 mm2

SOI−H9SOI1−After CMP−Metal 1

Adder

HSOI9 After CMP-metal1

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General Overview of the Adder - Testability

0.25V 1.2V 1.2V

RIPPLE-CARRY 32-BITS ADDER

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Testability - Level shifters

Adder input level shifter to shift the voltage from 1.2V to 0.4V Adder output level shifter to shift the supply voltage from 0.4V to 1.2V

0.4V 1.2V 1.2V

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Adder functionality tests

Test timing period : 300 ns Adder supply voltage : 1.2 V to 0.2 V Conclusion: Adders using high speed transistors are functionnal for supply voltages down to 0.25V Adders using low leakage transistors are functionnal for supply voltages down to 0.5V

Nmos Pmos 1.2V 0.5V 0.45V 0.4V 0.3V 0.25V 0.24V 0.23V high speed floating body / DTMOS 0.2V

• 0.3V

FUNCTIONAL 1 error 3 errors high speed floating body only FUNCTIONAL 1 error high speed DTMOS only FUNCTIONAL 2 errors low leakage DTMOS only 0.3V

• 0.4V

FUNC- TIONAL 1 error 3 errors

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Adders delay time measurements

For supply voltages below0.5V (normal use of DTMOS), the DTMOS only adder is found to be faster than the other adders. The high speed circuit is faster than the low leakage circuit.

50 100 150 200 250 300 350 0,25 0,3 0,4 0,6 0,8 1 1,2 TaddFb TaddBc 50 100 150 200 250 300 0,25 0,3 0,4 0,5 0,6 0,8 1 1,2 TaddHS TaddLL

Tadd(ns) Tadd(ns) Vdd(V) Vdd(V)

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Adders standby current

Standby current increases in the DTMOS circuit for supply voltages

• ver 0.6V due to direct bias of body/source diodes

.

0.25 0.3 0.4 0.6 0.8

1

1.2 1.00E−007 1.00E−006 1.00E−005 1.00E−004

IstdbyFb IstdbyBc

Vdd (V)

Istandby (A)

Source/body leakage

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Conclusion

Aim : To evaluate DTMOS performances for low voltage digital applications ☞ Comparison of SOI DTMOS and Floating Body implementations ☞ 32-bits adder Results : ☞ SOI can provide ulta low voltage operation with floating body transistors or DTMOS ☞ DTMOS can be used to reduce circuits delays at very low voltage ☞ Layout area may be increased by using DTMOS transistors ☞ Power consumption may be increased by using DTMOS transistors ☞ For medium and low voltages, DTMOS shall be introduced

• nly on the most capacitive lines